参数资料
型号: DAC1208D750HN
厂商: NXP Semiconductors N.V.
元件分类: 外设及接口
英文描述: Dual 12-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating
封装: DAC1208D750HN/C1<SOT804-3|<<<1<Always Pb-free,;DAC1208D750HN/C1<SOT804-3|<<<1<Always Pb-free,;
文件页数: 18/98页
文件大小: 554K
代理商: DAC1208D750HN
DAC1208D750
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 6 December 2010
18 of 98
NXP Semiconductors
DAC1208D750
2
×
, 4
×
or 8
×
interpolating DAC with JESD204A
The MDS signal generated by the master DAC must reach all slaves within one DAC
output clock period. This induces PCB layout constraints for the MDS signal and also for
the clock distribution. Because trace lengths differ, the clock edges will reach each of the
DACs at different times.
The worst case clock skew is given by
δ
t
1
= PH01
PH03, where PH0x represents the
sum of the trace delay and the clock skew at the output of the clock generator.
The maximum allowable trace delay for the MDS signal is given by
Δ
t = TDAC
δ
t
1
.
Fig 9.
Clock skew case 1: Master is the farthest
001aal072
ref clock
TDAC
master clock
PH03
slave 1 clock
PH02
slave 2 clock
PH01
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