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| 型号： | DAC312HS-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/14页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT MULT HS 20-SOIC |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1,000 |
| 设置时间： | 250ns |
| 位数： | 12 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 双 ± |
| 功率耗散（最大）： | 375mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电流，单极；2 电流，双极 |
| 采样率（每秒）： | * |
DAC312
–10–
REV. C
APPLICATIONS INFORMATION
REFERENCE AMPLIFIER SETUP
The DAC312 is a multiplying D/A converter in which the out-
put current is the product of a digital number and the input ref-
erence current. The reference current may be fixed or may vary
from nearly zero to +1.0 mA. The full range output current is a
linear function of the reference current and is given by:
IFR =
4095
4096
× 4 × (I
REF) = 3.999 IREF,
where IREF = I14
In positive reference applications, an external positive reference
voltage forces current through R14 into the VREF(+) terminal
(pin 14) of the reference amplifier. Alternatively, a negative ref-
erence may be applied to VREF(–) at pin 15. Reference current
flows from ground through R14 into VREF(+) as in the positive
reference case. This negative reference connection has the ad-
vantage of a very high impedance presented at pin 15. The volt-
age at pin 14 is equal to and tracks the voltage at pin 15 due to
the high gain of the internal reference amplifier. R15 (nominally
equal to R14) is used to cancel bias current errors.
Bipolar references may be accommodated by offsetting VREF or
pin 15. The negative common-mode range of the reference am-
plifier is given by: VCM– = V– plus (IREF × 3 k) plus 1.23 V.
The positive common-mode range is V+ less 1.8 V.
When a dc reference is used, a reference bypass capacitor is rec-
ommended. A 5.0 V TTL logic supply is not recommended as a
reference. If a regulated power supply is used as a reference,
R14 should be split into two resistors with the junction bypassed
to ground with a 0.1
F capacitor.
For most applications the tight relationship between IREF and IFS
will eliminate the need for trimming IREF. If required, full scale
trimming may be accomplished by adjusting the value of R14,
or by using a potentiometer for R14. An improved method of
full-scale trimming which eliminates potentiometer T.C. effects
is shown in the Recommended Full-Scale Adjustment circuit.
The reference amplifier must be compensated by using a capaci-
tor from pin 16 to V–. For fixed reference operation, a 0.01
F
capacitor is recommended. For variable reference applications,
see section entitled “Reference Amplifier Compensation for
Multiplying Applications.”
MULTIPLYING OPERATION
The DAC312 provides excellent multiplying performance with
an extremely linear relationship between IFS and IREF over a
range of 1 mA to 1
A. Monotonic operation is maintained over
a typical range of IREF from 100
A to 1.0 mA. Although some
degradation of gain accuracy will be realized at reduced values
of IREF. (See Gain Accuracy vs. Reference Current).
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications will require the reference amplifier to
be compensated using a capacitor from pin 16 to V–. The value
of this capacitor depends on the impedance presented to pin 14
for R14 values of 1.0
, 2.5 and 5.0 k, minimum values of
CC are 5 pF, 10 pF, and 25 pF. Larger values of R14 require
proportionately increased values of CC for proper phase margin.
For fastest response to a pulse, low values of R14 enabling small
CC values should be used. If pin 14 is driven by a high imped-
ance such as a transistor current source, none of the above val-
ues will suffice and the amplifier must be heavily compensated
which will decrease overall bandwidth and slew rate. For R14 =
1 k
and C
C = 5 pF, the reference amplifier slews at 4 mA/s
enabling a transition from IREF = 0 to IREF = 1 mA in 250 ns.
Operation with pulse inputs to the reference amplifier may be
accommodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (IREF = 0) condition. Full-scale transition (0 mA to 1 mA)
occurs in 62.5 ns when the equivalent impedance at pin 14 is
800
and C
C = 0. This yields a reference slew rate of 8 mA/
s
which is relatively independent of RIN and VIN values.
LOGIC INPUTS
The DAC312 design incorporates a unique logic input circuit
which enables direct interface to all popular logic families and
provides maximum noise immunity. This feature is made pos-
sible by the large input swing capability, 40
A logic input cur-
rent, and completely adjustable logic threshold voltage. For V–
= –15 V, the logic inputs may swing between –5 V and +10 V.
This enables direct interface with +15 V CMOS logic, even
when the DAC312 is powered from a +5 V supply. Minimum
input logic swing and minimum logic threshold voltage are given
by: V– plus (IREF
× 3 k) plus 1.8 V. The logic threshold may
be adjusted over a wide range by placing an appropriate voltage
at the logic threshold control pin (pin 13, VLC). The appropriate
graph shows the relationship between VLC and VTH over the
temperature range, with VTH nominally 1.4 above VLC. For
TTL interface, simply ground pin 13. When interfacing ECL,
an IREF
≤ 1 mA is recommended. For interfacing other logic
families, see block titled “Interfacing With Various Logic Fami-
lies”. For general setup of the logic control circuit, it should be
noted that pin 13 will sink 7 mA typical; external circuitry
should be designed to accommodate this current.
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