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| 型号： | DAC312HS-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/14页 |
| 文件大小： | 0K |
| 描述： | IC DAC 12BIT MULT HS 20-SOIC |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 1,000 |
| 设置时间： | 250ns |
| 位数： | 12 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 双 ± |
| 功率耗散（最大）： | 375mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 20-SOIC W |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电流，单极；2 电流，双极 |
| 采样率（每秒）： | * |
DAC312
–11–
REV. C
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided
where IO + IO = IFR. Current appears at the true output when a
“1” is applied to each logic input. As the binary count increases,
the sink current at pin 18 increases proportionally, in the fash-
ion of a “positive logic” D/A converter. When a “0” is applied to
any input bit, that current is turned off at pin 18 and turned on
at pin 19. A decreasing logic count increases IO as in a negative
or inverted logic D/A converter. Both outputs may be used si-
multaneously. If one of the outputs is not required it must still
be connected to ground or to a point capable of sourcing IFR; do
not leave an unused output pin open.
Both outputs have an extremely wide voltage compliance en-
abling fast direct current-to-voltage conversion through a resis-
tor tied to ground or other voltage source. Positive compliance
is 25 V above V– and is independent of the positive supply.
Negative compliance is +10 V above V–.
The dual outputs enable double the usual peak-to-peak load
swing when driving loads in quasi-differential fashion. This fea-
ture is especially useful in cable driving, CRT deflection and in
other balanced applications such as driving center-tapped coils
and transformers.
POWER SUPPLIES
The DAC312 operates over a wide range of power supply volt-
ages from a total supply of 20 V to 36 V. When operating with
V– supplies of –10 V or less, IREF ≤ 1 mA is recommended. Low
reference current operation decreases power consumption and
increases negative compliance, reference amplifier negative
common-mode range, negative logic input range, and negative
logic threshold range; consult the various figures for guidance.
For example, operation at –9 V with IREF = 1 mA is not recom-
mended because negative output compliance would be reduced
to near zero. Operation from lower supplies is possible, however
at least 8 V total must be applied to insure turn-on of the inter-
nal bias network.
Symmetrical supplies are not required, as the DAC312 is quite
insensitive to variations in supply voltage. Battery operation is
feasible as no ground connection is required; however, an artifi-
cial ground may be used to insure logic swings, etc. remain be-
tween acceptable limits.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the
DAC312 are guaranteed to apply over the entire rated operating
temperature range. Full-scale output current drift is tight, typi-
cally
±10 ppm/°C, with zero-scale output current and drift es-
sentially negligible compared to 1/2 LSB.
The temperature coefficient of the reference resistor R14 should
match and track that of the output resistor for minimum overall
full-scale drift. Settling times of the DAC312 decrease approxi-
mately 10% at –55
°C; at +125°C an increase of about 15% is
typical.
SETTLING TIME
The DAC312 is capable of extremely fast settling times; typi-
cally 250 ns at IREF = 1.0 mA. Judicious circuit design and care-
ful board layout must be employed to obtain full performance
potential during testing and application. The logic switch design
enables propagation delays of only 25 ns for each of the 12 bits.
Settling time to within 1/2 LSB of the LSB is therefore 25 ns,
with each progressively larger bit taking successively longer. The
MSB settles in 250 ns, thus determining the overall settling time
of 250 ns. Settling to 10-bit accuracy requires about 90 ns to
130 ns. The output capacitance of the DAC312 including the
package is approximately 20 pF; therefore, the output RC time
constant dominates settling time if RL > 500
.
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values down to 0.5 mA, with gradual increases
for lower IREF values lies in the ability to attain a given output
level with lower load resistors, thus reducing the output RC
time constant.
Measurement of the settling time requires the ability to accu-
rately resolve
±1/2 LSB of current, which is ±500 nA for 4 mA
FSR. In order to assure the measurement is of the actual settling
time and not the RC time of the output network, the resistive
termination on the output of the DAC must be 500
or less.
This does, however, place certain limitations on the testing ap-
paratus. At IREF values of less than 0.5 mA, it is difficult to pre-
vent RC damping of the output and maintain adequate
sensitivity. Because the DAC312 has 8 equal current sources for
the 3 most significant bits, the major carry occurs at the code
change of 000111111111 to 111000000000. The worst case set-
tling time occurs at the zero to full-scale transition and it re-
quires 9.2 time constants for the DAC output to settle to within
±1/2 LSB (0.0125%) of its final value.
The DAC312 switching transients or “glitches” are on the order
of 500 mV-ns. This is most evident when switching through the
major carry and may be further reduced by adding small capaci-
tive loads at the output with a minor sacrifice in transition speeds.
Fastest operation can be obtained by using short leads, minimiz-
ing output capacitance and load resistor values, and by adequate
bypassing at the supply, reference, and VLC terminals. Supplies
do not require large electrolytic bypass capacitors as the supply
current drain is independent of input logic states; 0.1
F capaci-
tors at the supply pins provide full transient protection.
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