参数资料
型号: DAC5652AIPFBRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: DUAL, PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 10-BIT DAC, PQFP48
封装: GREEN, PLASTIC, TQFP-48
文件页数: 3/25页
文件大小: 511K
代理商: DAC5652AIPFBRG4
DA[9:0]
DB[9:0]
SLEEP
CLKA/B
WRTA/B
Internal
DigitalIn
DVDD
400W
100kW
DGND
GSET
MODE
Internal
DigitalIn
DVDD
400W
100kW
DGND
www.ti.com
SLAS535B – SEPTEMBER 2007 – REVISED DECEMBER 2010
Digital Inputs and Timing
Digital Inputs
The data input ports of the DAC5652A accept a standard positive coding with data bits DA9 and DB9 being the
most significant bits (MSB). The converter outputs support a clock rate of up to 275 MSPS. The best
performance is typically achieved with a symmetric duty cycle for write and clock; however, the duty cycle may
vary as long as the timing specifications are met. Similarly, the setup and hold times may be chosen within their
specified limits.
All digital inputs of the DAC5652A are CMOS compatible. Figure 13 and Figure 14 show schematics of the
equivalent CMOS digital inputs of the DAC5652A. The pullup and pulldown circuitry is approximately equivalent
to 100k
. The 10-bit digital data input follows the offset positive binary coding scheme. The DAC5652A is
designed to operate with a digital supply (DVDD) of 3 V to 3.6 V.
Figure 13. CMOS/TTL Digital Equivalent Input With Internal Pulldown Resistor
Figure 14. CMOS/TTL Digital Equivalent Input With Internal Pullup Resistor
Input Interfaces
The DAC5652A features two operating modes selected by the MODE pin, as shown in Table 1.
For dual-bus input mode, the device essentially consists of two separate DACs. Each DAC has its own
separate data input bus, clock input, and data write signal (data latch-in).
In single-bus interleaved mode, the data must be presented interleaved at the A-channel input bus. The
B-channel input bus is not used in this mode. The clock and write input are now shared by both DACs.
Copyright 2007–2010, Texas Instruments Incorporated
11
Product Folder Link(s): DAC5652A
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