参数资料
型号: DAC5652AIPFBRG4
厂商: TEXAS INSTRUMENTS INC
元件分类: DAC
英文描述: DUAL, PARALLEL, WORD INPUT LOADING, 0.02 us SETTLING TIME, 10-BIT DAC, PQFP48
封装: GREEN, PLASTIC, TQFP-48
文件页数: 4/25页
文件大小: 511K
代理商: DAC5652AIPFBRG4
DA[9:0]/DB[9:0]
tLAT
tPD
ts
WRTA/WRTB
CLKA/CLKB
IOUT
or
IOUT
tLPH
Valid Data
tsu
th
SLAS535B – SEPTEMBER 2007 – REVISED DECEMBER 2010
www.ti.com
Table 1. Operating Modes
MODE Pin
MODE pin connected to DGND
MODE pin connected to DVDD
Bus input
Single-bus interleaved mode, clock and write input equal for both DACs
Dual-bus mode, DACs operate independently
Dual-Bus Data Interface and Timing
In dual-bus mode, the MODE pin is connected to DVDD. The two converter channels within the DAC5652A
consist of two independent, 10-bit, parallel data ports. Each DAC channel is controlled by its own set of write
(WRTA, WRTB) and clock (CLKA, CLKB) lines. The WRTA/B lines control the channel input latches and the
CLKA/B lines control the DAC latches. The data is first loaded into the input latch by a rising edge of the
WRTA/B line.
The internal data transfer requires a correct sequence of write and clock inputs, since essentially two clock
domains having equal periods (but possibly different phases) are input to the DAC5652A. This is defined by a
minimum requirement of the time between the rising edge of the clock and the rising edge of the write inputs.
This essentially implies that the rising edge of CLKA/B must occur at the same time or before the rising edge of
the WRTA/B signal. A minimum delay of 2 ns must be maintained if the rising edge of the clock occurs after the
rising edge of the write. Note that these conditions are satisfied when the clock and write inputs are connected
externally. Note that all specifications were measured with the WRTA/B and CLKA/B lines connected together.
Figure 15. Dual-Bus Mode Operation
Single-Bus Interleaved Data Interface and Timing
In single-bus interleaved mode, the MODE pin is connected to DGND. Figure 16 shows the timing diagram. In
interleaved mode, the A- and B-channels share the write input (WRTIQ) and update clock (CLKIQ and internal
CLKDACIQ). Multiplexing logic directs the input word at the A-channel input bus to either the A-channel input
latch (SELECTIQ is high) or to the B-channel input latch (SELECTIQ is low). When SELECTIQ is high, the data
value in the B-channel latch is retained by presenting the latch output data to its input again. When SELECTIQ is
low, the data value in the A-channel latch is retained by presenting the latch output data to its input.
In interleaved mode, the A-channel input data rate is twice the update rate of the DAC core. As in dual-bus
mode, it is important to maintain a correct sequence of write and clock inputs. The edge-triggered flip-flops latch
the A- and B-channel input words on the rising edge of the write input (WRTIQ). This data is presented to the A-
and B-DAC latches on the following falling edge of the write inputs. The DAC5652A clock input is divided by a
factor of two before it is presented to the DAC latches.
12
Copyright 2007–2010, Texas Instruments Incorporated
Product Folder Link(s): DAC5652A
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