参数资料
型号: DAC5674IPHPRG4
厂商: Texas Instruments
文件页数: 17/39页
文件大小: 0K
描述: IC DAC 14BIT 400MSPS 48-HTQFP
产品培训模块: Data Converter Basics
标准包装: 1,000
系列: CommsDAC™
设置时间: 20ns
位数: 14
数据接口: 并联
转换器数目: 1
电压电源: 模拟和数字
功率耗散(最大): 550mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-TQFP 裸露焊盘
供应商设备封装: 48-HTQFP(7x7)
包装: 带卷 (TR)
输出数目和类型: 2 电流,单极
采样率(每秒): 400M
配用: 296-30860-ND - EVAL MODULE FOR DAC5674
DAC5674
SLWS148A SEPTEMBER 2003 REVISED OCTOBER 2005
www.ti.com
24
Clock Input and Timing
Figure 27 shows the clock and data input timing diagram for internal and external clock modes, respectively.
Note that a negative value indicates a reversal of the edge positions as shown in the timing diagram. Figure 27
also shows the delay (td) of the 1×/2× data clock (PLLLOCK) from CLK in external clock mode (typical td = 4.1
ns). The latency from data to DAC is defined by Figure 28. The DAC5674 features a differential clock input.
In internal clock mode, the internal data clock is a divided down version of the PLL clock (/2 or /4), depending
on the level of interpolation (2
× or 4×). In external mode, the internal data clock is a divided down version of
the input CLK (/2 or /4), depending on the level of interpolation (2
× or 4×). Internal edge-triggered flip-flops latch
the input word on the rising edge of the positive data clock.
CLKC
PLLLOCK
D[13:0]
Valid Data
CLK
CLKC
D[13:0]
Valid Data
th
tsu
tlph
th
tsu
td_clk
Figure 27. Internal (Left) and External (Right) Clock Mode Timing
2x Interpolation
4x Interpolation
DAC
0
2000
3FFF
0
2000
0
Typical tsu = 0.5 ns, th = 0.1 ns
Typical tsu = 2.9 ns, th = 2.3 ns, td = 3.6 ns
D[13:0]
tlat_nx
Figure 28. Data to DAC Latency
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