参数资料
型号: DAC5674IPHPRG4
厂商: Texas Instruments
文件页数: 24/39页
文件大小: 0K
描述: IC DAC 14BIT 400MSPS 48-HTQFP
产品培训模块: Data Converter Basics
标准包装: 1,000
系列: CommsDAC™
设置时间: 20ns
位数: 14
数据接口: 并联
转换器数目: 1
电压电源: 模拟和数字
功率耗散(最大): 550mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-TQFP 裸露焊盘
供应商设备封装: 48-HTQFP(7x7)
包装: 带卷 (TR)
输出数目和类型: 2 电流,单极
采样率(每秒): 400M
配用: 296-30860-ND - EVAL MODULE FOR DAC5674
DAC5674
SLWS148A SEPTEMBER 2003 REVISED OCTOBER 2005
www.ti.com
30
DESIGNING THE PLL LOOP FILTER
The DAC5674 contains an external loop filter to set the bandwidth and phase margin of the PLL. For the external
second-order filter shown in Figure 38, the components R1, C1, and C2 are set by the user to optimize the PLL
for the application. The resistance R3 = 200
. and the capacitance C3 = 8 pF are internal to the DAC5674.
Note that R1 and C1 can be reversed.
R3
C3
R1
C1
C2
External
Internal
Figure 38. DAC5674 Loop Filter
0
50
100
150
200
250
300
350
400
450
500
0
100
200
300
400
500
600
Typical DAC5674 Gvco at 25
5C
Frequency MHz
VCO
Gain
MHz
Figure 39. Typical VCO Gain vs VCO Frequency at 25
°C
The typical VCO gain (Gvco) (the slope of VCO frequency vs voltage) as a function of VCO frequency for the
DAC5674 is shown in Figure 39. For the lowest possible phase noise, the VCO frequency should be chosen
so Gvco is minimized, where
Fvco = Fdata
× Interpolation × PLL Divider:
For example, if Fdata = 100 MSPS and 2
× interpolation is used, the PLL divider should be set to 2 to lock the
VCO at 400 MHz for a typical Gvco of 210 MHz/V. Note that the maximum specified VCO frequency range is
160 MHz to 400 MHz.
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