参数资料
型号: DAC8248FSZ-REEL
厂商: Analog Devices Inc
文件页数: 15/16页
文件大小: 0K
描述: IC DAC 12BIT DUAL W/BUFF 24SOIC
产品培训模块: Data Converter Fundamentals
DAC Architectures
标准包装: 1,000
设置时间: 1µs
位数: 12
数据接口: 并联
转换器数目: 2
电压电源: 单电源
功率耗散(最大): 50µW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SOIC(0.295",7.50mm 宽)
供应商设备封装: 24-SOIC W
包装: 带卷 (TR)
输出数目和类型: 2 电流,单极;2 电流,双极
采样率(每秒): 1M
DAC8248
–8–
REV. B
Four Cycle Update
Five Cycle Update
Write Timing Cycle Diagram
PARAMETER DEFINITIONS
RESOLUTION (N)
The resolution of a DAC is the number of states (2
n) that the
full-scale range (FSR) is divided (or resolved) into; where n is
equal to the number of bits.
RELATIVE ACCURACY (INL)
Relative accuracy, or integral nonlinearity, is the maximum de-
viation of the analog output (from the ideal) from a straight line
drawn between the end points. It is expressed in terms of least
significant bit (LSB), or as a percent of full scale.
DIFFERENTIAL NONLINEARITY (DNL)
Differential nonlinearity is the worst case deviation of any adja-
cent analog output from the ideal 1 LSB step size. The devia-
tion of the actual “step size” from the ideal step size of 1 LSB is
called the differential nonlinearity error or DNL. DACs with
DNL greater than
±1 LSB may be nonmonotonic. ±1/2 LSB
INL guarantees monotonicity and
±1 LSB maximum DNL.
GAIN ERROR (GFSE)
Gain error is the difference between the actual and the ideal
analog output range, expressed as a percent of full-scale or in
terms of LSB value. It is the deviation in slope of the DAC
transfer characteristic from ideal.
Refer to PMI 1990/91 Data Book, Section 11, for additional
digital-to-analog converter definitions.
GENERAL CIRCUIT DESCRIPTION
CONVERTER SECTION
The DAC8248 incorporates two multiplying 12-bit current out-
put CMOS digital-to-analog converters on one monolithic chip.
It contains two highly stable thin-film R-2R resistor ladder net-
works, two 12-bit DAC registers, two 8-bit input registers, and
two 4-bit input registers. It also contains the DAC control logic
circuitry and 24 single-pole, double-throw NMOS transistor
current switches.
Figure 1 shows a simplified circuit for the R-2R ladder and tran-
sistor switches for a single DAC. R is typically 11 k
. The tran-
sistor switches are binarily scaled in size to maintain a constant
voltage drop across each switch. Figure 2 shows a single NMOS
transistor switch.
Figure 1. Simplified Single DAC Circuit Configuration.
(Switches Are Shown For All Digital Inputs at Zero)
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