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参数资料
| 型号： | DAC8551IADGKR |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO8 |
| 封装： | GREEN, PLASTIC, MSOP-8 |
| 文件页数： | 20/24页 |
| 文件大小： | 456K |
| 代理商： | DAC8551IADGKR |
www.ti.com
SERIAL WRITE OPERATION
SCLK
1
24
SYNC
D
IN
DB23
DB0
DB23
t
8
t
6
t
3
t
2
t
1
t
7
t
9
t
5
t
4
TIMING CHARACTERISTICS
(1) (2)
SLAS429B – APRIL 2005 – REVISED OCTOBER 2006
V
DD = 2.7V to 5.5V, all specifications –40°C to +105°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 2.7V to 3.6V
50
t1(3)
SCLK cycle time
ns
VDD = 3.6V to 5.5V
33
VDD = 2.7V to 3.6V
13
t2
SCLK HIGH time
ns
VDD = 3.6V to 5.5V
13
VDD = 2.7V to 3.6V
22.5
t3
SCLK LOW time
ns
VDD = 3.6V to 5.5V
13
VDD = 2.7V to 3.6V
0
t4
SYNC to SCLK rising edge setup time
ns
VDD = 3.6V to 5.5V
0
VDD = 2.7V to 3.6V
5
t5
Data setup time
ns
VDD = 3.6V to 5.5V
5
VDD = 2.7V to 3.6V
4.5
t6
Data hold time
ns
VDD = 3.6V to 5.5V
4.5
VDD = 2.7V to 3.6V
0
t7
24th SCLK falling edge to SYNC rising edge
ns
VDD = 3.6V to 5.5V
0
VDD = 2.7V to 3.6V
50
t8
Minimum SYNC HIGH time
ns
VDD = 3.6V to 5.5V
33
t9
24th SCLK falling edge to SYNC falling edge
VDD = 2.7V to 5.5V
100
ns
(1)
All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2)
(3)
Maximum SCLK frequency is 30MHz at VDD = 3.6V to 5.5V and 20MHz at VDD = 2.7V to 3.6V.
5
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