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参数资料
型号： DAC8564ICPWR
厂商： TEXAS INSTRUMENTS INC
元件分类： DAC
英文描述： SERIAL INPUT LOADING, 12 us SETTLING TIME, 16-BIT DAC, PDSO16
封装： GREEN, PLASTIC, TSSOP-16
文件页数： 49/51页
文件大小： 1549K
代理商： DAC8564ICPWR
DAC8564
www.ti.com
SBAS403D
– JUNE 2007 – REVISED MAY 2011
TIMING REQUIREMENTS
(1) (2)
At AVDD = IOVDD= 2.7V to 5.5V and –40°C to +105°C range (unless otherwise noted).
DAC8564
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IOVDD = AVDD = 2.7V to 3.6V
40
t1
(3)
SCLK cycle time
ns
IOVDD = AVDD = 3.6V to 5.5V
20
IOVDD = AVDD = 2.7V to 3.6V
20
t2
SCLK HIGH time
ns
IOVDD = AVDD = 3.6V to 5.5V
10
IOVDD = AVDD = 2.7V to 3.6V
20
t3
SCLK LOW time
ns
IOVDD = AVDD = 3.6V to 5.5V
10
IOVDD = AVDD = 2.7V to 3.6V
0
t4
SYNC to SCLK rising edge setup time
ns
IOVDD = AVDD = 3.6V to 5.5V
0
IOVDD = AVDD = 2.7V to 3.6V
5
t5
Data setup time
ns
IOVDD = AVDD = 3.6V to 5.5V
5
IOVDD = AVDD = 2.7V to 3.6V
4.5
t6
Data hold time
ns
IOVDD = AVDD = 3.6V to 5.5V
4.5
IOVDD = AVDD = 2.7V to 3.6V
0
t7
SCLK falling edge to SYNC rising edge
ns
IOVDD = AVDD = 3.6V to 5.5V
0
IOVDD = AVDD = 2.7V to 3.6V
40
t8
Minimum SYNC HIGH time
ns
IOVDD = AVDD = 3.6V to 5.5V
20
IOVDD = AVDD = 2.7V to 3.6V
130
t9
24th SCLK falling edge to SYNC falling edge
ns
IOVDD = AVDD = 3.6V to 5.5V
130
IOVDD = AVDD = 2.7V to 3.6V
15
SYNC rising edge to 24th SCLK falling edge
t10
ns
(for successful SYNC interrupt)
IOVDD = AVDD = 3.6V to 5.5V
15
IOVDD = AVDD = 2.7V to 3.6V
15
t11
ENABLE falling edge to SYNC falling edge
ns
IOVDD = AVDD = 3.6V to 5.5V
15
IOVDD = AVDD = 2.7V to 3.6V
10
t12
24th SCLK falling edge to ENABLE rising edge
ns
IOVDD = AVDD = 3.6V to 5.5V
10
IOVDD = AVDD = 2.7V to 3.6V
50
t13
24th SCLK falling edge to LDAC rising edge
ns
IOVDD = AVDD = 3.6V to 5.5V
50
IOVDD = AVDD = 2.7V to 3.6V
10
t14
LDAC rising edge to ENABLE rising edge
ns
IOVDD = AVDD = 3.6V to 5.5V
10
IOVDD = AVDD = 2.7V to 3.6V
10
t15
LDAC HIGH time
ns
IOVDD = AVDD = 3.6V to 5.5V
10
(1)
All input signals are specified with tR = tF = 3ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
(2)
See the Serial Write Operation timing diagram.
(3)
Maximum SCLK frequency is 50MHz at IOVDD = VDD = 3.6V to 5.5V and 25MHz at IOVDD = AVDD = 2.7V to 3.6V.
Copyright
2007–2011, Texas Instruments Incorporated
7
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