参数资料
型号: DC1082A-B
厂商: Linear Technology
文件页数: 7/24页
文件大小: 0K
描述: BOARD SAR ADC LTC1407A
软件下载: QuikEval II System
设计资源: DC1082A Design File
DC1082A Schematic
标准包装: 1
系列: QuikEval-II™
ADC 的数量: 1
位数: 14
采样率(每秒): 3M
数据接口: 串行,SPI?
输入范围: 0 ~ 2.5 V
已用 IC / 零件: LTC1407
已供物品:
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LTC1407/LTC1407A
15
1407fb
APPLICATIONS INFORMATION
POWER-DOWN MODES
Upon power-up, the LTC1407/LTC1407A are initialized to
the active state and are ready for conversion. The Nap and
Sleep mode waveforms show the power-down modes for
the LTC1407/LTC1407A. The SCK and CONV inputs control
the power-down modes (see Timing Diagrams). Two ris-
ing edges at CONV, without any intervening rising edges
at SCK, put the LTC1407/LTC1407A in Nap mode and the
power drain drops from 14mW to 6mW. The internal refer-
ence remains powered in Nap mode. One or more rising
edges at SCK wake up the LTC1407/LTC1407A for service
very quickly and CONV can start an accurate conversion
within a clock cycle.
Four rising edges at CONV, without any intervening rising
edges at SCK, put the LTC1407/LTC1407A in Sleep mode
and the power drain drops from 14mW to 10μW. To bring
the part out of Sleep mode requires one or more rising SCK
edges followed by a Nap request. Then one or more rising
edges at SCK wake up the LTC1407/LTC1407A for operation.
When Nap mode is entered after Sleep mode, the reference
that was shut down in Sleep mode is reactivated.
The internal reference (VREF ) takes 2ms to slew and settle
with a 10μF load. Using Sleep mode more frequently com-
promises the settled accuracy of the internal reference.
Note that for slower conversion rates, the Nap and Sleep
modes can be used for substantial reductions in power
consumption.
Figure 5. Recommended Layout
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