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参数资料
| 型号： | DC1227A |
| 厂商： | Linear Technology |
| 文件页数： | 7/20页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR LTC3534 |
| 设计资源： | DC1227A Design Files DC1227A Schematic |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步升/步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 5V |
| 电流 - 输出： | 500mA（最小值） |
| 输入电压： | 3.6 ~ 7 V |
| 稳压器拓扑结构： | 降压-升压 |
| 频率 - 开关： | 1MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTC3534 |
LTC3534
PIN FUNCTIONS
V OUT = 1.000 ?
R1 + R2
GNDPads(Pins1,8,9,16;GNPackage): ICSubstrate
Grounds. These pins MUST be soldered to the printed
circuit board ground to provide both electrical contact
and a good thermal contact to the PCB.
RUN/SS (Pin 2): Combined Shutdown and Soft-Start. Ap-
plying a voltage below 400mV shuts down the IC. Apply
a voltage above 1.4V to enable the IC and above 2.4V to
ensure that the error amp is not clamped from soft-start.
An R-C from the enable command signal to this pin will
provide a soft-start function by limiting the rise time of
the V C pin. PWM mode operation must be commanded
to properly enable the IC.
GND (Pin 3): Signal Ground for the IC.
PGND1, PGND2 (Pins 4, 7): Power Ground for the Internal
N-channel MOSFET Power Switches (Switches B and C).
SW1 (Pin 5): Switch Pin where Internal Switches A and
B are Connected. Connect inductor from SW1 to SW2.
Minimize trace length to reduce EMI.
SW2 (Pin 6): Switch Pin where Internal Switches C and
D are Connected. Minimize trace length to reduce EMI.
PWM (Pin 10): Burst Mode Select. PWM must be driven
HIGH during start-up. When V OUT is in regulation, the
PWM pin may be driven LOW to command Burst Mode
operation. Applying a voltage below 400mV enables Burst
Mode operation, providing a significant efficiency improve-
ment at light loads. Burst Mode operation will continue
until this pin is driven high. Applying a voltage above 1.4V
disables Burst Mode operation, enabling low noise, fixed
frequency operation.
V OUT (Pin 11): Output of the Synchronous Rectifier. A filter
capacitor is placed from V OUT to GND. A ceramic bypass
capacitor is recommended as close to the V OUT and GND
pins as possible. V OUT is given by the following equation:
V
R2
PV IN (Pin 12): Power V IN Supply Pin. A 10μF ceramic
capacitor is recommended as close to the PV IN and PGND
pins as possible.
V IN (Pin 13): Input Supply Pin. Connect the power source
to this pin.
V C (Pin 14): Error Amp Output. An R-C network is con-
nected from this pin to FB for loop compensation. Refer
to “Closing the Feedback Loop” section for component
selection guidelines.
FB (Pin 15): Feedback Pin. Connect V OUT resistor divider
tap to this pin. The output voltage can be adjusted from
1.8V to 7V. The feedback reference voltage is typically 1V.
Exposed Pad (Pin 17; DHC Package): IC Substrate Ground.
This pin MUST be soldered to the printed circuit board
ground to provide both electrical contact and a good
thermal contact to the PCB.
3534fb
For more information www.linear.com/LTC3534
7
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