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| 型号： | DC1278A |
| 厂商： | Linear Technology |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2351-14 |
| 软件下载： | QuikEval II System |
| 设计资源： | DC1278A Design File DC1278A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval-II™ |
| ADC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 1.5M |
| 数据接口： | 串行，SPI? |
| 输入范围： | 0 ~ 2.5 V |
| 在以下条件下的电源（标准）： | 16.5mW @ 1.5MSPS |
| 已用 IC / 零件： | LTC2351-14 |
| 已供物品： | 板 |
| 相关产品： | LTC2351HUH-14#PBF-ND - IC ADC 14BIT 1.5MSPS 32-QFN LTC2351HUH-12#PBF-ND - IC ADC 12BIT 1.5MSPS 32-QFN LTC2351HUH-14#TRPBF-ND - IC ADC 14BIT 1.5MSPS 32-QFN LTC2351HUH-12#TRPBF-ND - IC ADC 12BIT 1.5MSPS 32-QFN LTC2351CUH-12#TRPBF-ND - IC ADC 12BIT 1.5MSPS 32-QFN LTC2351IUH-14#TRPBF-ND - IC ADC 14BIT 1.5MSPS 32-QFN LTC2351IUH-12#TRPBF-ND - IC ADC 12BIT 1.5MSPS 32-QFN LTC2351CUH-14#TRPBF-ND - IC ADC 14BIT 1.5MSPS 32-QFN LTC2351CUH-12#PBF-ND - IC ADC 12BIT 1.5MSPS 32-QFN LTC2351IUH-12#PBF-ND - IC ADC 12BIT 1.5MSPS 32-QFN 更多... |
LTC2351-14
17
235114fb
APPLICATIONS INFORMATION
and then buffer this signal with the appropriate number of
inverters to drive the serial clock input of the processor
serial port. Use the falling edge of the clock to latch data
from the serial data output (SDO) into your processor
serial port. The 14-bit serial data will be received in six
16-bit words with 96 or more clocks per frame sync. If
fewer than six channels are selected by SEL0–SEL2 for
conversion, then 16 clocks are needed per channel to
convert the analog inputs and read out the resulting data
after the next convert pulse. It is good practice to drive the
LTC2351-14 SCK input rst to avoid digital noise interfer-
ence during the internal bit comparison decision by the
internal high speed comparator. Unlike the CONV input,
the SCK input is not sensitive to jitter because the input
signal is already sampled and held constant.
Serial Data Output (SDO)
Upon power-up, the SDO output is automatically reset to
the high impedance state. The SDO output remains in high
impedance until a new conversion is started. SDO sends out
up to six sets of 14 bits in the output data stream after the
third rising edge of SCK after the start of conversion with
the rising edge of CONV. The six, or fewer, 14-bit words are
separated by two don’t care bits and two clock cycles in
high impedance mode. Please note the delay specication
from SCK to a valid SDO. SDO is always guaranteed to
be valid by the next rising edge of SCK. The 16- to 96-bit
output data stream is compatible with the 16-bit or 32-bit
serial port of most processors.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC2351-14, a printed circuit board
with ground plane is required. Layout for the printed circuit
board should ensure that digital and analog signal lines
are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track. If optimum phase match between the
inputs is desired, the length of the twelve input wires of
the six input channels should be kept matched. But each
pair of input wires to the six input channels should be
kept separated by a ground trace to avoid high frequency
crosstalk between channels.
High quality tantalum and ceramic bypass capacitors
should be used at the VCC, VDD and VREF pins, as shown
in the Block Diagram on the rst page of this data sheet.
For optimum performance, a 10μF surface mount tantalum
capacitor with a 0.1μF ceramic is recommended for the
VCC, VDD and VREF pins. Alternatively, 10μF ceramic chip
capacitors such as X5R or X7R may be used. The capaci-
tors must be located as close to the pins as possible. The
traces connecting the pins and the bypass capacitors must
be kept short and should be made as wide as possible. The
VCC and VDD bypass capacitor returns to the ground plane
and the VREF bypass capacitor returns to the Pin 22. Care
should be taken to place the 0.1μF VCC and VDD bypass
capacitor as close to Pins 24 and 25 as possible.
Figure 6 shows the recommended system ground connec-
tions. All analog circuitry grounds should be terminated at
the LTC2351-14 Exposed Pad. The ground return from the
LTC2351-14 to the power supply should be low impedance
for noise-free operation. The Exposed Pad of the 32-pin
QFN package is also internally tied to the ground pads.
The Exposed Pad should be soldered on the PC board to
reduce ground connection inductance. All ground pins
(GND, DGND, OGND) must be connected directly to the
same ground plane under the LTC2351-14.
VDD BYPASS,
0.1μF, 0402
OVDD BYPASS,
0.1μF, 0402
VREF BYPASS,
10μF, 0805
VCC BYPASS,
0.1μF, 0402 AND
10μF, 0805
235114 F06
Figure 6. Recommended Layout
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