参数资料
型号: DC1337A
厂商: Linear Technology
文件页数: 6/26页
文件大小: 0K
描述: BOARD SAR ADC LTC2309
软件下载: QuikEval System
设计资源: DC1337A Design File
DC1337A Schematic
标准包装: 1
系列: QuikEval™
ADC 的数量: 1
位数: 12
采样率(每秒): 14k
数据接口: I²C,串行
在以下条件下的电源(标准): 1.5mW @ 1kSPS
已用 IC / 零件: LTC2309
已供物品:
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LTC2309
2309fd
Internal Conversion Clock
The internal conversion clock is factory trimmed to
achieveatypicalconversiontime(tCONV)of1.3μsand
a maximum conversion time of 1.8μs over the full
operatingtemperaturerange.
I2C Interface
TheLTC2309communicatesthroughanI2Cinterface.
TheI2Cinterfaceisa2-wireopen-draininterfacesup-
porting multiple devices and multiple masters on a
singlebus.Theconnecteddevicescanonlypullthe
serialdataline(SDA)LOWandcanneverdriveitHIGH.
SDAisrequiredtobeexternallyconnectedtothesup-
plythroughapull-upresistor.Whenthedatalineisnot
beingdrivenLOW,itisHIGH.DataontheI2Cbuscan
betransferredatratesupto100kbits/sinthestandard
modeandupto400kbits/sinthefastmode.TheVDD
powershouldnotberemovedfromtheLTC2309when
theI2CbusisactivetoavoidloadingtheI2Cbuslines
throughtheinternalESDprotectiondiodes.
EachdeviceontheI2Cbusisrecognizedbyaunique
addressstoredinthedeviceandcanonlyoperateeither
asatransmitterorreceiver,dependingonthefunction
ofthedevice.Adevicecanalsobeconsideredasa
masteroraslavewhenperformingdatatransfers.A
masteristhedevicewhichinitiatesadatatransferon
thebusandgeneratestheclocksignalstopermitthe
transfer.Devicesaddressedbythemasterareconsid-
eredslaves.
TheLTC2309canonlybeaddressedasaslave(see
Table2).Onceaddressed,itcanreceiveconfiguration
bits(DINword)ortransmitthelastconversionresult.The
serialclockline(SCL)isalwaysaninputtotheLTC2309
andtheserialdataline(SDA)isbidirectional.Thedevice
supportsthestandardmodeandthefastmodefordata
transferspeedsupto400kbits/s(seetheTimingDiagram
sectionfordefinitionoftheI2Ctiming).
The START and STOP Conditions
ReferringtoFigure7,aSTART(S)conditionisgener-
atedbytransitioningSDAfromHIGHtoLOWwhile
SCLisHIGH.Thebusisconsideredtobebusyafterthe
STARTcondition.Whenthedatatransferisfinished,a
STOP(P)conditionisgeneratedbytransitioningSDA
fromLOWtoHIGHwhileSCLisHIGH.Thebusisfree
afteraSTOPconditionisgenerated.STARTandSTOP
conditionsarealwaysgeneratedbythemaster.
When the bus is in use, it stays busy if a repeated
START(Sr)isgeneratedinsteadofaSTOPcondition.
TherepeatedSTARTtimingisfunctionallyidenticalto
theSTARTandisusedforwritingandreadingfromthe
devicebeforetheinitiationofanewconversion.
AppLICAtIOns InFORMAtIOn
S
START Condition
STOP Condition
P
2309 F07
SDA
SCL
SDA
SCL
Figure 7. Timing Diagrams of START and STOP Conditions
Data Transferring
AftertheSTARTcondition,theI2Cbusisbusyand
datatransfercanbeginbetweenthemasterandthe
addressedslave.Dataistransferredoverthebusin
groups of nine bits, one byte followed by one ac-
knowledge(ACK)bit.ThemasterreleasestheSDA
lineduringtheninthSCLclockcycle.Theslavedevice
canissueanACKbypullingSDALOWorissueaNot
Acknowledge (NACK) by leaving the SDA line high
impedance(theexternalpull-upresistorwillholdthe
linehigh).ChangeofdataonlyoccurswhiletheSCL
lineisLOW.
Data Format
After a START condition, the master sends a 7-bit
addressfollowedbyaread/write(R/W)bit.TheR/W
bitis1forareadrequestand0forawriterequest.
If the 7-bit address matches one of the LTC2309’s
9pin-selectableaddresses,theADCisselected.When
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