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参数资料
| 型号： | DC1369A-C |
| 厂商： | Linear Technology |
| 文件页数： | 8/34页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 80MSPS LTC2259-14 |
| 软件下载： | QuikEval II System |
| 设计资源： | DC1369A Design Files |
| 标准包装： | 1 |
| 系列： | * |
| 相关产品： | DC890B-ND - BOARD USB DATA COLLECTION |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
LTC2261-14
LTC2260-14/LTC2259-14
16
226114fc
For more information www.linear.com/LTC2261-14
pin FuncTions
FULL-RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0 to D13 (Pins 17-24, 29-34): Digital Outputs. D13 is
the MSB.
CLKOUT– (Pin 27): Inverted Version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
of CLKOUT+. The phase of CLKOUT+ can also be delayed
relative to the digital outputs by programming the mode
control registers.
DNC (Pin 35): Do not connect this pin.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE-DATA RATE CMOS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
OVDD)
D0_1 to D12_13 (Pins 18, 20, 22, 24, 30, 32, 34): Double-
Data Rate Digital Outputs. Two data bits are multiplexed onto
eachoutputpin.Theevendatabits(D0,D2,D4,D6,D8,D10,
D12) appear when CLKOUT+ is low. The odd data bits (D1,
D3, D5, D7, D9, D11, D13) appear when CLKOUT+ is high.
CLKOUT– (Pin 27): Inverted Version of CLKOUT+.
CLKOUT+ (Pin 28): Data Output Clock. The digital outputs
normally transition at the same time as the falling and ris-
ing edges of CLKOUT+. The phase of CLKOUT+ can also
be delayed relative to the digital outputs by programming
the mode control registers.
DNC (Pins 17, 19, 21, 23, 29, 31, 33, 35): Do not con-
nect these pins.
OF (Pin 36): Over/Under Flow Digital Output. OF is high
when an overflow or underflow has occurred.
DOUBLE-DATA RATE LVDS OUTPUT MODE
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100 Termination Resistor Between the Pins
of Each LVDS Output Pair.
D0_1–/D0_1+ to D12_13–/D12_13+ (Pins 17/18, 19/20,
21/22, 23/24, 29/30, 31/32, 33/34): Double-Data Rate
Digital Outputs. Two data bits are multiplexed onto each
differential output pair. The even data bits (D0, D2, D4,
D6, D8, D10, D12) appear when CLKOUT+ is low. The odd
data bits (D1, D3, D5, D7, D9, D11, D13) appear when
CLKOUT+ is high.
CLKOUT–/CLKOUT+ (Pins 27/28): Data Output Clock.
The digital outputs normally transition at the same time
as the falling and rising edges of CLKOUT+. The phase of
CLKOUT+ can also be delayed relative to the digital outputs
by programming the mode control registers.
OF–/OF+ (Pins 35/36): Over/Under Flow Digital Output.
OF+ is high when an overflow or underflow has occurred.
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相关代理商/技术参数 |
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| DC1369A-D | 制造商:Linear Technology 功能描述:14BIT ADC Eval Brd, Rq. DC1371 & DC1075 制造商:Linear Technology 功能描述:14BIT ADC Eval Brd, Rq. DC1371 & DC1075; Silicon Manufacturer:Linear Technology; Silicon Core Number:LTC2258-14; Kit Application Type:Data Converter; Application Sub Type:ADC; Kit Contents:Board, Guide |
| DC1369A-E | 制造商:Linear Technology 功能描述:14BIT ADC Eval Brd, Rq. DC1371 & DC1075 制造商:Linear Technology 功能描述:14BIT ADC Eval Brd, Rq. DC1371 & DC1075; Silicon Manufacturer:Linear Technology; Silicon Core Number:LTC2257-14; Kit Application Type:Data Converter; Application Sub Type:ADC; Kit Contents:Board, Guide |
| DC1369A-F | 制造商:Linear Technology 功能描述:14BIT ADC Eval Brd, Rq. DC1371 & DC1075 制造商:Linear Technology 功能描述:14BIT ADC Eval Brd, Rq. DC1371 & DC1075; Silicon Manufacturer:Linear Technology; Silicon Core Number:LTC2256-14; Kit Application Type:Data Converter; Application Sub Type:ADC; Kit Contents:Board, Guide |
| DC1369A-G | 功能描述:BOARD DEMO 125MSPS LTC2261-12 RoHS:是 类别:未定义的类别 >> 其它 系列:* 标准包装:1 系列:* 其它名称:MS305720A |
| DC1369A-H | 功能描述:BOARD DEMO 105MSPS LTC2260-12 RoHS:是 类别:未定义的类别 >> 其它 系列:* 标准包装:1 系列:* 其它名称:MS305720A |
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