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参数资料
| 型号： | DC1384A-A |
| 厂商： | Linear Technology |
| 文件页数： | 3/22页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2452 |
| 软件下载： | QuikEval System |
| 设计资源： | DC1384A Design File DC1384A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 2 |
| 位数： | 16 |
| 采样率（每秒）： | 60 |
| 数据接口： | 串行，SPI? |
| 输入范围： | ±VREF |
| 已用 IC / 零件： | LTC2452 |
| 已供物品： | 板 |
| 相关产品： | LTC2452ITS8#TRPBF-ND - IC ADC 16BIT DELTA SIG TSOT23-8 LTC2452ITS8#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG TSOT23-8 LTC2452IDDB#TRPBF-ND - IC ADC 16BIT DELTA SIG 8-DFN LTC2452IDDB#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 8-DFN LTC2452CTS8#TRPBF-ND - IC ADC 16BIT DELTA SIG TSOT23-8 LTC2452CTS8#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG TSOT23-8 LTC2452CDDB#TRPBF-ND - IC ADC 16BIT DELTA SIG 8-DFN LTC2452CDDB#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 8-DFN |
LTC2452
11
2452fd
For more information www.linear.com/LTC2452
applicaTions inForMaTion
based upon external timing. The user then pulls CS low
(CS =
↓) and uses 16 clock cycles to transfer the result.
Followingthe16thrisingedgeoftheclock,CSispulledhigh
(CS =
↑), which triggers a new conversion.
ThetimingdiagraminFigure9isidenticaltothatofFigure 8,
except in this case a new conversion is triggered by SCK.
The 16th SCK falling edge triggers a new conversion cycle
and the CS signal is subsequently pulled high.
Examples of Aborting Cycle Using CS
For some applications, the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2452 is in
the data output state, a CS rising edge clears the remain-
ing data bits from the output registers, aborts the output
cycle and triggers a new conversion. Figure 10 shows
an example of aborting an I/O with idle-high (CPOL = 1)
and Figure 11 shows an example of aborting an I/O with
idle-low (CPOL = 0).
A new conversion cycle can be triggered using the CS
signal without having to generate any serial clock pulses
as shown in Figure 12. If SCK is maintained at a low logic
level, after the end of a conversion cycle, a new conver-
sion operation can be triggered by pulling CS low and
then high. When CS is pulled low (CS = LOW), SDO will
output the sign (D15) of the result of the just completed
conversion. While a low logic level is maintained at SCK
Figure 9. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion
Figure 8. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion
D15
D14
D13
D12
D2
D1
D0
clk1
clk2
clk3
clk4 clk14 clk15 clk16
SCK
SD0
CONVERT
SLEEP
DATA OUTPUT
2452 F08
CS
D15
D14
D13
D12
D2
D1
D0
SD0
clk1
clk2
clk3
clk4
clk15
clk14
clk16
SCK
CONVERT
SLEEP
DATA OUTPUT
2452 F09
CS
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