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参数资料
| 型号： | DC1384A-A |
| 厂商： | Linear Technology |
| 文件页数： | 5/22页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2452 |
| 软件下载： | QuikEval System |
| 设计资源： | DC1384A Design File DC1384A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 2 |
| 位数： | 16 |
| 采样率（每秒）： | 60 |
| 数据接口： | 串行，SPI? |
| 输入范围： | ±VREF |
| 已用 IC / 零件： | LTC2452 |
| 已供物品： | 板 |
| 相关产品： | LTC2452ITS8#TRPBF-ND - IC ADC 16BIT DELTA SIG TSOT23-8 LTC2452ITS8#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG TSOT23-8 LTC2452IDDB#TRPBF-ND - IC ADC 16BIT DELTA SIG 8-DFN LTC2452IDDB#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 8-DFN LTC2452CTS8#TRPBF-ND - IC ADC 16BIT DELTA SIG TSOT23-8 LTC2452CTS8#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG TSOT23-8 LTC2452CDDB#TRPBF-ND - IC ADC 16BIT DELTA SIG 8-DFN LTC2452CDDB#TRMPBFTR-ND - IC ADC 16BIT DELTA SIG 8-DFN |
LTC2452
13
2452fd
For more information www.linear.com/LTC2452
pin and CS is subsequently pulled high (CS = HIGH) the
remaining 15 bits of the result (D14:D0) are discarded
and a new conversion cycle starts.
Following the aborted I/O, additional clock pulses in the
CONVERT state are acceptable, but excessive signal tran-
sitions on SCK can potentially create noise on the ADC
during the conversion, and thus may negatively influence
the conversion accuracy.
2-Wire Operation
The 2-wire operation modes, while reducing the number
of required control signals, should be used only if the
LTC2452 low power sleep capability is not required. In
addition the option to abort serial data transfers is no
longer available. Hardwire CS to GND for 2-wire operation.
Figure 13 shows a 2-wire operation sequence which uses
an idle-high (CPOL = 1) serial clock signal. The conversion
Figure 13. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation Example
status can be monitored at the SDO output. Following a
conversion cycle, the ADC enters SLEEP state and the
SDO output transitions from HIGH to LOW. Subsequently
16 clock pulses are applied to the SCK input in order
to serially shift the 16 bit result. Finally, the 17th clock
pulse is applied to the SCK input in order to trigger a new
conversion cycle.
Figure 14 shows a 2-wire operation sequence which uses
an idle-low (CPOL = 0) serial clock signal. The conversion
status cannot be monitored at the SDO output. Following
a conversion cycle, the LTC2452 bypasses the SLEEP
state and immediately enters the DATA OUTPUT state. At
this moment the SDO pin outputs the sign (D15) of the
conversion result. The user must use external timing in
order to determine the end of conversion and result avail-
ability. Subsequently 16 clock pulses are applied to SCK
in order to serially shift the 16-bit result. The 16th clock
falling edge triggers a new conversion cycle.
applicaTions inForMaTion
Figure 14. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation Example
2452 F13
D15
D14
D13
D12
D2
D1
D0
SD0
clk1
clk2
clk3
clk4
clk15
clk16
clk17
SCK
CONVERT
SLEEP
DATA OUTPUT
CS = LOW
2452 F14
D15
D14
D13
D12
D2
D1
D0
SD0
CS = LOW
clk1
clk2
clk3
clk14
clk4
clk15
clk16
SCK
CONVERT
DATA OUTPUT
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