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参数资料
| 型号： | DC1444A-B |
| 厂商： | Linear Technology |
| 文件页数： | 9/26页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2305 |
| 软件下载： | QuikEval System |
| 设计资源： | DC1444A Design File DC1444A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 2 |
| 位数： | 12 |
| 采样率（每秒）： | 14k |
| 数据接口： | I²C，串行 |
| 在以下条件下的电源（标准）： | 1.5mW @ 1kSPS |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2305 |
| 已供物品： | 板 |
| 相关产品： | LTC2305IMS#TRPBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305IDE#TRPBF-ND - IC ADC 12-BIT 2CHN 12-DFN LTC2305IDE#PBF-ND - IC ADC 12-BIT 2CHN 12-DFN LTC2305HMS#TRPBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305HMS#PBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305CMS#TRPBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305CMS#PBF-ND - IC ADC 12-BIT 2CHN 12-MSOP LTC2305CDE#TRPBF-ND - IC ADC 12-BIT 2CHN 12-DFN LTC2305CDE#PBF-ND - IC ADC 12-BIT 2CHN 12-DFN LTC2305IMS#PBF-ND - IC ADC 12BIT I2C 12-MSOP |
LTC2301/LTC2305
17
23015fb
APPLICATIONS INFORMATION
Output Data Format
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters either nap or sleep mode depending on the
setting of the SLP bit (see Nap Mode and Sleep Mode
sections). When the LTC2301/LTC2305 is addressed for a
read operation, it acknowledges by pulling SDA LOW and
acts as a transmitter. The master/receiver can read up to
two bytes from the LTC2301/LTC2305. After a complete
read operation of 2 bytes, a STOP condition is needed to
initiate a new conversion. The device will NACK subsequent
read operations while a conversion is being performed.
The data output stream is 16 bits long and is shifted out
on the falling edges of SCL (see Figure 7a). The rst bit
is the MSB and the 12th bit is the LSB of the conversion
result. The remaining four bits are zero. Figures 13 and 14
are the transfer characteristics for the bipolar and unipolar
modes. Data is output on the SDA line in 2’s complement
format for bipolar readings and in straight binary for
unipolar readings.
Input Data Format
When the LTC2301/LTC2305 is addressed for a write op-
eration, it acknowledges by pulling SDA LOW during the
LOW period before the 9th cycle and acts as a receiver.
The master/transmitter can then send 1 byte to program
the device. The input byte consists of the 6-bit DIN word
followed by two bits that are ignored by the ADC and are
considered don’t cares (X) (see Figure 7b). The input bits
are latched on the rising edge of SCL during the write
operation.
Figure 7a. Timing Diagram for Reading from the LTC2301/LTC2305
12
A6
SDA
START BY
MASTER
ACK BY
ADC
ACK BY
MASTER
NACK BY
MASTER
STOP
BY MASTER
CONVERSION
INITIATED
SCL
(CONTINUED)
A5
A4
A3
A2
A1
A0
R/W
3456789
123456789
23015 F07a
B11
B10
READ 1 BYTE
B9
B8
B7
MOST SIGNIFICANT DATA BYTE
B6
B5
B4
SDA
(CONTINUED)
B3
B2
B1
B0
LEAST SIGNIFICANT DATA BYTE
READ 1 BYTE
ADDRESS FRAME
Figure 7b. Timing Diagram for Writing to the LTC2301/LTC2305
12
A6
SDA
START BY
MASTER
ACK BY
ADC
ACK BY
ADC
CONVERSION
INITIATED
STOP BY
MASTER
SCL
A5
A4
A3
A2
A1
A0
R/W
3456789
123456789
23015 F07b
S/D
O/S
WRITE 1 BYTE
X
UNI
DIN WORD
SLP
X
ADDRESS FRAME
NOTE: S/D BIT IS A DON’T CARE (X) FOR THE LTC2301
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