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参数资料
| 型号： | DC1525A-E |
| 厂商： | Linear Technology |
| 文件页数： | 17/34页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO 40MSPS LTC2171-14 |
| 软件下载： | QuikEval II System |
| 设计资源： | DC1525A Design Files |
| 标准包装： | 1 |
| 系列： | * |
| 相关产品： | DC1371A-ND - BOARD USB DATA ACQUISITION HS |
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LTC2172-14/
LTC2171-14/LTC2170-14
24
21721014fb
applicaTions inForMaTion
By default the outputs are standard LVDS levels: a 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100 differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
The outputs are powered by OVDD and OGND which are
isolated from the A/D core power and ground.
Programmable LVDS Output Current
Thedefaultoutputdrivercurrentis3.5mA.Thiscurrentcan
be adjusted by control register A2 in serial programming
mode.Availablecurrentlevelsare1.75mA,2.1mA,2.5mA,
3mA, 3.5mA, 4mA and 4.5mA. In parallel programming
mode the SCK pin can select either 3.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100 termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100 termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing. In
parallel programming mode the SDO pin enables internal
termination. Internal termination should only be used with
1.75mA, 2.1mA or 2.5mA LVDS output current modes.
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2172-14. The Sampling
Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2171-14) or 25MHz (LTC2170-14).
SERIALIZATION MODE
MAXIMUM SAMPLING
FREQUENCY, fS (MHz)
DCO FREQUENCY
FR FREQUENCY
SERIAL DATA RATE
2-Lane
16-Bit Serialization
65
4 fS
fS
8 fS
2-Lane
14-Bit Serialization
65
3.5 fS
0.5 fS
7 fS
2-Lane
12-Bit Serialization
65
3 fS
fS
6 fS
1-Lane
16-Bit Serialization
62.5
8 fS
fS
16 fS
1-Lane
14-Bit Serialization
65
7 fS
fS
14 fS
1-Lane
12-Bit Serialization
65
6 fS
fS
12 fS
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
Table 2. Output Codes vs Input Voltage
AIN+ – AIN–
(2V RANGE)
D13-D0
(OFFSET BINARY)
D13-D0
(2’s COMPLEMENT)
>1.000000V
+0.999878V
+0.999756V
11 1111 1111 1111
11 1111 1111 1110
01 1111 1111 1111
01 1111 1111 1110
+0.000122V
+0.000000V
–0.000122V
–0.000244V
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
–0.999878V
–1.000000V
≤–1.000000V
00 0000 0000 0001
00 0000 0000 0000
10 0000 0000 0001
10 0000 0000 0000
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones in
the ADC output spectrum. These unwanted tones can be
randomized by randomizing the digital output before it is
transmitted off chip, which reduces the unwanted tone
amplitude.
The digital output is randomized by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
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