参数资料
型号: DC1562A-J
厂商: Linear Technology
文件页数: 22/26页
文件大小: 0K
描述: BOARD EVAL LTC6993-4
设计资源: DC1562A Design Files
DC1562A Schematic
特色产品: TimerBlox?
标准包装: 1
系列: TimerBlox®
主要目的: 定时,单稳多谐振荡器
嵌入式:
已用 IC / 零件: LTC6993-4
主要属性: 下降沿触发器,可再触发
次要属性: 2.25 V ~ 5.5 V 电源
已供物品:
LTC6993-1/LTC6993-2
LTC6993-3/LTC6993-4
5
69931234fb
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC6993C is guaranteed functional over the operating
temperature range of –40°C to 85°C.
Note 3: The LTC6993C is guaranteed to meet specified performance from
0°C to 70°C. The LTC6993C is designed, characterized and expected to
meet specified performance from –40°C to 85°C but it is not tested or
QA sampled at these temperatures. The LTC6993I is guaranteed to meet
specified performance from –40°C to 85°C. The LTC6993H is guaranteed
to meet specified performance from –40°C to 125°C. The LTC6993MP is
guaranteed to meet specified performance from –55°C to 125°C.
Note 4: Pulse width accuracy is defined as the deviation from the tOUT
equation, assuming RSET is used to program the pulse width.
Note 5: See Operation section, Table 1 and Figure 2 for a full explanation
of how the DIV pin voltage selects the value of DIVCODE.
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Test conditions are V+ = 2.25V to 5.5V, TRIG = 0V, DIVCODE = 0 to 15
(NDIV = 1 to 221), RSET = 50k to 800k, RLOAD = ∞, CLOAD = 5pF unless otherwise noted.
Note 6: The TRIG pin has hysteresis to accommodate slow rising or falling
signals. The threshold voltages are proportional to V+. Typical values can
be estimated at any supply voltage using:
VTRIG(RISING) ≈ 0.55 V+ + 185mV and
VTRIG(FALLING) ≈ 0.48 V+ – 155mV
Note 7: To conform to the Logic IC Standard, current out of a pin is
arbitrarily given a negative value.
Note 8: Output rise and fall times are measured between the 10% and the
90% power supply levels with 5pF output load. These specifications are
based on characterization.
Note 9: Settling time is the amount of time required for the output to settle
within ±1% of the final pulse width after a 0.5
× or 2× change in ISET.
Note 10: Jitter is the ratio of the deviation of the output pulse width to the
mean of the pulse width. This specification is based on characterization
and is not 100% tested.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tPD
Trigger Propagation Delay
V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
11
17
28
ns
tWIDTH
Minimum Recognized TRIG Pulse Width
V+ = 3.3V
5
ns
tARM
Recovery Time (LTC6993-1/LTC6993-3)
–4
ns
tRETRIG
Time Between Trigger Signals
(LTC6993-2/LTC6993-4)
NDIV = 1
V+ = 3.3V
NDIV > 1
V+ = 3.3V
10
50
ns
tr
Output Rise Time (Note 8)
V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.1
1.7
2.7
ns
tf
Output Fall Time (Note 8)
V+ = 5.5V
V+ = 3.3V
V+ = 2.25V
1.0
1.6
2.4
ns
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