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| 型号： | DC1571A-C |
| 厂商： | Linear Technology |
| 文件页数： | 20/24页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC2381-16 |
| 软件下载： | QuikEval II System |
| 设计资源： | DC1571A Design Files DC1571A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 250k |
| 数据接口： | 串行，SPI? |
| 输入范围： | ±2.5 V |
| 在以下条件下的电源（标准）： | 3.25mW @ 250kSPS |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2381-16 |
| 已供物品： | 板 |
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LTC2381-16
5
238116f
ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
tSCKH
SCK High Time
l
4ns
tSCKL
SCK Low Time
l
4ns
tSSDISCK
SDI Setup Time From SCK ↑
(Note 11)
l
4ns
tHSDISCK
SDI Hold Time From SCK ↑
(Note 11)
l
1ns
tSCKCH
SCK Period in Chain Mode
tSCKCH = tSSDISCK + tDSDO (Note 11)
l
13.5
ns
tDSDO
SDO Data Valid Delay from SCK ↑
CL = 20pF (Note 11)
l
9.5
ns
tHSDO
SDO Data Remains Valid Delay from SCK ↑
CL = 20pF (Note 10)
l
1ns
tDSDOBUSYL
SDO Data Valid Delay from BUSY ↓
CL = 20pF (Note 10)
l
5ns
tEN
Bus Enable Time After RDL ↓
(Note 11)
l
16
ns
tDIS
Bus Relinquish Time After RDL ↑
(Note 11)
l
13
ns
tSSCKRDL
SCK Setup Time from RDL/SDI ↓
(Note 10)
l
1ns
tHSCKRDL
SCK Hold Time from RDL/SDI ↓
(Note 10)
l
16
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to ground.
Note 3: When these pin voltages are taken below ground or above REF
or OVDD, they will be clamped by internal diodes. This product can handle
input currents up to 100mA below ground or above REF or OVDD without
latch-up.
Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 2.5V, fSMPL = 250kHz.
Note 5: Recommended operating conditions.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: Bipolar zero-scale error is the offset voltage measured from
–0.5LSB when the output code flickers between 0000 0000 0000 0000
and 1111 1111 1111 1111. Full-scale bipolar error is the worst-case of
–FS or +FS untrimmed deviation from ideal first and last code transitions
and includes the effect of offset error.
Note 8: All specifications in dB are referred to a full-scale ±2.5V input with
a 2.5V reference voltage.
Note 9: fSMPL = 250kHz, IREF varies proportionately with sample rate.
Note 10: Guaranteed by design, not subject to test.
Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V
and OVDD = 5.25V.
Note 12: tSCK of 10ns maximum allows a shift clock frequency up to
100MHz for rising capture.
0.8*OVDD
0.2*OVDD
50%
238216 F01
0.2*OVDD
0.8*OVDD
0.2*OVDD
0.8*OVDD
tDELAY
tWIDTH
tDELAY
Figure 1. Voltage Levels for Timing Specifications
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