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参数资料
| 型号： | DC1621A |
| 厂商： | Linear Technology |
| 文件页数： | 17/24页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO LTM8062 |
| 设计资源： | DC1621A Design Files |
| 标准包装： | 1 |
| 系列： | LTM®, uModule® |
| 主要目的： | 电源管理，电池充电器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | LTM8062 |
| 主要属性： | 2 芯锂离子电池 / 锂聚合物，7.2V 2A 输出 |
| 次要属性： | 9.75V ~ 32V 输入 |
| 已供物品： | 板 |
| 相关产品： | LTM8062EV#PBF-ND - IC BATTERY CHARGER TRACK 77-LGA LTM8062IV#PBF-ND - IC BATTERY CHARGER TRACK 77-LGA |
LTM8062/LTM8062A
APPLICATIONS INFORMATION
1. Place the C IN capacitor as close as possible to the V IN
and GND connection of the LTM8062/LTM8062A.
2. If used, place the C BAT capacitor as close as possible to
the BAT and GND connection of the LTM8062/LTM8062A.
3. Place the C IN and C BAT (if used) capacitors such that their
ground current flows directly adjacent or underneath
the LTM8062/LTM8062A.
4. Connect all of the GND connections to as large a copper
pour or plane area as possible on the top layer. Avoid
breaking the ground connection between the external
components and the LTM8062/LTM8062A.
5. For good heat sinking, use vias to connect the GND
copper area to the board’s internal ground planes.
Liberally distribute these GND vias to provide both a
good ground connection and thermal path to the internal
planes of the printed circuit board. Pay attention to the
location and density of the thermal vias in Figure 5. The
LTM8062/LTM8062A can benefit from the heat-sinking
afforded by vias that connect to internal GND planes at
these locations, due to their proximity to internal power
handling components. The optimum number of thermal
vias depends upon the printed circuit board design.
For example, a board might use very small via holes.
It should employ more thermal vias than a board that
uses larger holes.
Hot-Plugging Safely
The small size, robustness and low impedance of ceramic
capacitors make them an attractive option for the input
bypass capacitor of LTM8062/LTM8062A. However, these
capacitors can cause problems if the LTM8062/LTM8062A
are plugged into a live input supply (see Application Note
88 for a complete discussion). The low loss ceramic
capacitor combined with stray inductance in series with
the power source forms an underdamped tank circuit,
and the voltage at the V IN pin of the LTM8062/LTM8062A
can ring to more than twice the nominal input voltage,
possibly exceeding the LTM8062/LTM8062A’s rating and
damage the part. If the input supply is poorly controlled
or the user will be plugging the LTM8062/LTM8062A into
an energized supply, the input network should be designed
to prevent this overshoot. This can be accomplished by
installing a small resistor in series with V IN , but the most
popular method of controlling input voltage overshoot is
to add an electrolytic bulk capacitor to the V IN net. This
capacitor’s relatively high equivalent series resistance
damps the circuit and eliminates the voltage overshoot.
The extra capacitor improves low frequency ripple filter-
ing and can slightly improve the efficiency of the circuit,
though it is physically large.
Parallel Operation
If more current is desired, multiple LTM8062/LTM8062As
may be paralleled, as shown in the Typical Applications
section. When doing so, bear in mind the following:
1. Each LTM8062/LTM8062A ADJ pin requires 250k input
resistance as described in the ADJ pin function descrip-
tion. Table 1 gives the recommended resistor network
for a single LTM8062/LTM8062A. If using more than
one, either apply one network of the appropriate value
to each LTM8062/LTM8062A’s ADJ pin or apply a single
network, each resistor value divided by the number of
paralleled LTM8062/LTM8062As and connect all of the
ADJ pins together.
2. Tie the BAT outputs directly together. Apply the same
output capacitance to each LTM8062/LTM8062A as if
it were used as a single device and not paralleled.
3. The individual LTM8062/LTM8062As may not share
current equally as the battery nears the float voltage.
Thermal Considerations
The thermal performance of the LTM8062/LTM8062A is
given in the Typical Performance Characteristics section.
These curves were generated by the LTM8062/LTM8062A
mounted to a 58cm 2 4-layer FR4 printed circuit board.
Boards of other sizes and layer count can exhibit differ-
ent thermal behavior, so it is incumbent upon the user to
verify proper operation over the intended system’s line,
load and environmental operating conditions.
For increased accuracy and fidelity to the actual application,
many designers use FEA to predict thermal performance.
To that end, the Pin Configuration section of the data sheet
typically gives four thermal coefficients:
8062fd
For more information www.linear.com/LTM8062
17
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