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参数资料
| 型号： | DC887A |
| 厂商： | Linear Technology |
| 文件页数： | 20/20页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC1408 |
| 软件下载： | QuikEval II System |
| 设计资源： | DC887A Design File DC887A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval-II™ |
| ADC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 600k |
| 数据接口： | 串行 |
| 输入范围： | ±1.25 V |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC1408 |
| 已供物品： | 板 |
| 相关产品： | LTC1408CUH-ND - IC ADC 14BIT 600KSPS 32-QFN LTC1408CUH-12#TRPBF-ND - IC ADC 12BIT 600KSPS 32-QFN LTC1408IUH-12#TRPBF-ND - IC ADC 12BIT 600KSPS 32-QFN LTC1408IUH#TRPBF-ND - IC ADC 14BIT 600KSPS 32-QFN LTC1408CUH#TRPBF-ND - IC ADC 14BIT 600KSPS 32-QFN LTC1408IUH-12#PBF-ND - IC ADC 12BIT 600KSPS 32-QFN LTC1408CUH-12#PBF-ND - IC ADC 12BIT 600KSPS 32-QFN LTC1408IUH#PBF-ND - IC ADC 14BIT 600KSPS 32-QFN LTC1408CUH#PBF-ND - IC ADC 14BIT 600KSPS 32-QFN |
9
LTC1408
1408fa
BLOCK DIAGRA
W
2
OGND
1
SD0
3
OVDD
3V
–
+
4
5
24
23
S & H
–
+
7
6
9
12 13
16
19
8
S & H
GND
EXPOSED PAD
VREF
10
F
CH0–
CH0+
CH1–
CH1+
–
+
10
11
S & H
–
+
14
15
S & H
CH2–
CH2+
CH3–
CH3+
–
+
17
18
S & H
–
+
20
21
S & H
CH4–
CH4+
CH5–
CH5+
10
F
0.1
F
LTC1408
DGND
32
SCK
30
CONV
SEL2 SEL1 SEL0
THREE-
STATE
SERIAL
OUTPUT
PORT
MUX
2.5V
REFERENCE
TIMING
LOGIC
VCC
25
3V
VDD
1408 BD
600ksps
14-BIT ADC
14-BIT LATCH 5
14-BIT LATCH 4
14-BIT LATCH 3
14-BIT LATCH 2
14-BIT LATCH 1
14-BIT LATCH 0
26
27
BIP
29
28
31
22
33
0.1
F
CONV (Pin 30): Convert Start. Holds the six analog input
signals and starts the conversion on the rising edge. Two
pulses with SCK in fixed high or fixed low state starts Nap
mode. Four or more pulses with SCK in fixed high or fixed
low state starts Sleep mode.
DGND (Pin 31): Digital Ground. This ground pin must be
tied directly to the solid ground plane. Digital input signal
currents flow through this pin.
SCK (Pin 32): External Clock Input. Advances the conver-
sion process and sequences the output data at SD0 (Pin1)
on the rising edge. One or more pulses wake from sleep
or nap power saving modes. 16 clock cycles are needed
for each of the channels that are activated by SELx (Pins
26, 27, 28), up to a total of 96 clock cycles needed to
convert and read out all 6 channels.
EXPOSED PAD (Pin 33): GND. Must be tied directly to the
solid ground plane.
UU
U
PI FU CTIO S
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