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参数资料
| 型号： | DC887A |
| 厂商： | Linear Technology |
| 文件页数： | 8/20页 |
| 文件大小： | 0K |
| 描述： | BOARD SAR ADC LTC1408 |
| 软件下载： | QuikEval II System |
| 设计资源： | DC887A Design File DC887A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval-II™ |
| ADC 的数量： | 1 |
| 位数： | 12 |
| 采样率（每秒）： | 600k |
| 数据接口： | 串行 |
| 输入范围： | ±1.25 V |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC1408 |
| 已供物品： | 板 |
| 相关产品： | LTC1408CUH-ND - IC ADC 14BIT 600KSPS 32-QFN LTC1408CUH-12#TRPBF-ND - IC ADC 12BIT 600KSPS 32-QFN LTC1408IUH-12#TRPBF-ND - IC ADC 12BIT 600KSPS 32-QFN LTC1408IUH#TRPBF-ND - IC ADC 14BIT 600KSPS 32-QFN LTC1408CUH#TRPBF-ND - IC ADC 14BIT 600KSPS 32-QFN LTC1408IUH-12#PBF-ND - IC ADC 12BIT 600KSPS 32-QFN LTC1408CUH-12#PBF-ND - IC ADC 12BIT 600KSPS 32-QFN LTC1408IUH#PBF-ND - IC ADC 14BIT 600KSPS 32-QFN LTC1408CUH#PBF-ND - IC ADC 14BIT 600KSPS 32-QFN |
16
LTC1408
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APPLICATIO S I FOR ATIO
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POWER-DOWN MODES
Upon power-up, the LTC1408 is initialized to the active
state and is ready for conversion. The Nap and Sleep mode
waveforms show the power down modes for the LTC1408.
The SCK and CONV inputs control the power down modes
(see Timing Diagrams). Two rising edges at CONV, with-
out any intervening rising edges at SCK, put the LTC1408
in Nap mode and the power drain drops from 15mW to
3.3mW. The internal reference remains powered in Nap
mode. One or more rising edges at SCK wake up the
LTC1408 for service very quickly and CONV can start an
accurate conversion within a clock cycle. Four rising
edges at CONV, without any intervening rising edges at
SCK, put the LTC1408 in Sleep mode and the power drain
drops from 15mW to 10
W. One or more rising edges at
SCK wake up the LTC1408 for operation. The internal
reference (VREF ) takes 2ms to slew and settle with a 10F
load. Using sleep mode more frequently compromises the
accuracy of the output data. Note that for slower conver-
sion rates, the Nap and Sleep modes can be used for
substantial reductions in power consumption.
DIGITAL INTERFACE
The LTC1408 has a 3-wire SPI (Serial Peripheral Interface)
interface. The SCK and CONV inputs and SDO output
implement this interface. The SCK and CONV inputs
accept swings from 3V logic and are TTL compatible, if the
logic swing does not exceed VDD. A detailed description of
the three serial port signals follows:
Conversion Start Input (CONV)
The rising edge of CONV starts a conversion, but subse-
quent rising edges at CONV are ignored by the LTC1408
until the following 96 SCK rising edges have occurred. The
duty cycle of CONV can be arbitrarily chosen to be used as
a frame sync signal for the processor serial port. A simple
approach to generate CONV is to create a pulse that is one
SCK wide to drive the LTC1408 and then buffer this signal
to drive the frame sync input of the processor serial port.
It is good practice to drive the LTC1408 CONV input first
to avoid digital noise interference during the sample-to-
hold transition triggered by CONV at the start of conver-
sion. It is also good practice to keep the width of the low
portion of the CONV signal greater than 15ns to avoid
introducing glitches in the front end of the ADC just before
the sample-and-hold goes into Hold mode at the rising
edge of CONV.
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