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参数资料
| 型号： | DC979A |
| 厂商： | Linear Technology |
| 文件页数： | 17/32页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2442 |
| 软件下载： | QuikEval System |
| 设计资源： | DC979A Design File DC979A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 8k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2442 |
| 已供物品： | 板 |
| 相关产品： | LTC2442IG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP LTC2442CG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP LTC2442IG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP LTC2442CG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP |
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LTC2442
24
2442fa
For more information www.linear.com/LTC2442
Input Bandwidth and Frequency Rejection
The combined effect of the internal SINC4 digital filter and
the digital and analog autocalibration circuits determines
theLTC2442inputbandwidthandrejectioncharacteristics.
The digital filter’s response can be adjusted by setting
the oversample ratio (OSR) through the SPI interface or
by supplying an external conversion clock to the fO pin.
Table 7 lists the properties of the LTC2442 with various
combinations of oversample ratio and clock frequency.
Understanding these properties is the key to fine tuning
the characteristics of the LTC2442 to the application.
Maximum Conversion Rate
The maximum conversion rate is the fastest possible rate
at which conversions can be performed.
First Notch Frequency
ThisisthefirstnotchintheSINC4portionofthedigitalfilter
anddependsonthefoclockfrequencyandtheoversample
ratio. Rejection at this frequency and its multiples (up to
the modulator sample rate of 1.8MHz) exceeds 120dB.
This is 8 times the maximum conversion rate.
Effective Noise Bandwidth
TheLTC2442hasextremelygoodinputnoiserejectionfrom
the first notch frequency all the way out to the modulator
sample rate (typically 1.8MHz). Effective noise bandwidth
is a measure of how the ADC will reject wideband input
noise up to the modulator sample rate.
Table 7
Over-
sample
Ratio
(OSR)
*RMS
Noise
ENOB
(VREF = 5V)
Maximum
Conversion Rate
First Notch
Frequency
Effective
Noise BW
–3dB
point (Hz)
Internal
9MHz clock
External
f0
Internal
9MHz clock
External
f0
Internal
9MHz clock
External
f0
Internal
9MHz clock
External
f0
64
23V
17.7
3515.6
f0/2560
28125
f0/320
3148
f0/5710
1696
f0/5310
128
3.6V
20.4
1757.8
f0/5120
14062.5
f0/640
1574
f0/2860
848
f0/10600
256
2.1V
21.2
878.9
f0/10240
7031.3
f0/1280
787
f0/1140
424
f0/21200
512
1.5V
21.6
439.5
f0/20480
3515.6
f0/2560
394
f0/2280
212
f0/42500
1024
1.2V
22
219.7
f0/40960
1757.8
f0/5120
197
f0/4570
106
f0/84900
2048
840nV
22.5
109.9
f0/81920
878.9
f0/1020
98.4
f0/9140
53
f0/170000
4096
630nV
22.4
54.9
f0/163840
439.5
f0/2050
49.2
f0/18300
26.5
f0/340000
8192
430nV
23.5
27.5
f0/327680
219.7
f0/4100
24.6
f0/36600
13.2
f0/679000
16384
305nV
24
13.7
f0/655360
109.9
f0/8190
12.4
f0/73100
6.6
f0/1358000
32768
220nV
24.4
6.9
f0/1310720
54.9
f0/16380
6.2
f0/146300
3.3
f0/2717000
*ADC noise increases by approximately √2 when OSR is decreased by a factor of 2 for OSR 32768 to OSR 256. The ADC noise at OSR 64 include effects
from internal modulator quantization noise.
29
2
30
1
36
6
7
35
3
2442 F14
34
4,5,32
REFERENCE
VOLTAGE
0.1V TO VCC
ANALOG INPUT
–0.5VREF TO
0.5VREF
3-WIRE
SPI INTERFACE
4.5V TO 5.5V
31
VCC
BUSY
FO
REF+
SCK
CH0
CH1
SDO
GND
CS
EXT
LTC2442
REF–
1F
0.1F
LTC1799
OUT
DIV
SET
GND
V+
RSET
NC
Figure 14. Simple External Clock Source
applications inForMation
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