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参数资料
| 型号： | DC979A |
| 厂商： | Linear Technology |
| 文件页数： | 4/32页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2442 |
| 软件下载： | QuikEval System |
| 设计资源： | DC979A Design File DC979A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 8k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2442 |
| 已供物品： | 板 |
| 相关产品： | LTC2442IG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP LTC2442CG#TRPBF-ND - IC ADC 24BIT 250MSPS 36-SSOP LTC2442IG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP LTC2442CG#PBF-ND - IC ADC 24BIT 4CH 36-SSOP |
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LTC2442
12
2442fa
For more information www.linear.com/LTC2442
the first falling edge of SCK. The final data bit (Bit 0) is
shifted out on the falling edge of the 31st SCK and may
be latched on the rising edge of the 32nd SCK pulse. On
the falling edge of the 32nd SCK pulse, SDO goes HIGH
indicating the initiation of a new conversion cycle. This
bit serves as EOC (Bit 31) for the next conversion cycle.
Table 2 summarizes the output data format.
As long as the voltage on the SEL+ and SEL– pins is main-
tained within the –0.3V to (VCC + 0.3V) absolute maximum
operating range, a conversion result is generated for any
differential input voltage VIN from –FS = –0.5 VREF to
+FS = 0.5 VREF. For differential input voltages greater
than +FS, the conversion result is clamped to the value
corresponding to the +FS + 1LSB. For differential input
voltages below –FS, the conversion result is clamped to
the value corresponding to –FS – 1LSB.
Serial Interface Pins
The LTC2442 transmits the conversion result and receives
the start of conversion command through a synchronous
3- or 4-wire interface. During the conversion and sleep
states, this interface can be used to access the converter
status and during the data output state it is used to read
the conversion result and program the speed, resolution
and input channel.
Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 1) is used to
synchronize the data transfer. Each bit of data is shifted
out the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2442 creates its own serial clock. In
the External SCK mode of operation, the SCK pin is used
as input. The internal or external SCK mode is selected
by tying EXT (Pin 3) LOW for external SCK and HIGH for
internal SCK.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 36), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO
pin is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 35) is HIGH, the SDO driver is switched
to a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
Table 2. LTC2442 Output Data Format
Differential Input Voltage
VIN*
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
Bit 27
Bit 26
Bit 25
...
Bit 0
VIN* ≥ 0.5 VREF**
0
1
0
...
0
0.5 VREF** –1LSB
0
1
0
1
...
1
0.25 VREF**
0
1
0
1
0
...
0
0.25 VREF** –1LSB
0
1
0
1
...
1
0
1
0
...
0
–1LSB
0
1
...
1
–0.25 VREF**
0
1
0
...
0
–0.25 VREF** –1LSB
0
1
0
1
...
1
–0.5 VREF**
0
1
0
...
0
VIN* < –0.5 VREF**
0
1
...
1
*The differential input voltage VIN = SEL+ – SEL–. **The differential reference voltage VREF = REF+ – REF–.
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