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参数资料
| 型号： | DDC112U/1K |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | ADC |
| 英文描述： | 2-CH 20-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO28 |
| 封装： | GREEN, PLASTIC, SOIC-28 |
| 文件页数： | 5/34页 |
| 文件大小： | 776K |
| 代理商： | DDC112U/1K |
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DDC112
13
SBAS085B
www.ti.com
TEST and CONV work together to implement this feature.
The test mode is entered when TEST is HIGH prior to a
CONV edge. At that point, a CONV edge triggers the ground-
ing of the analog inputs and the switching of 13pC packets
of charge onto the integration capacitors. If TEST is kept
HIGH through at least two conversions (that is, a rise and fall
of CONV), all four integrators will be charged with a 13pC
packet. At the end of each conversion, the voltage at the
output of the integrators is digitized as discussed in the
Continuous and Non-Continuous Operational Modes section
of this data sheet. The test mode is exited when TEST is
LOW and a CONV edge occurs.
Once the test mode is entered as described above, TEST
can cycle as many times as desired. When this is done,
additional 13pC packets are added on the rising edge of
TEST to the existing charge on the integrator capacitors.
Multiple charge packets can be added in this way as long as
the TEST pin is not LOW when CONV toggles.
DIGITAL ISSUES
The digital interface of the DDC112 provides the digital results
via a synchronous serial interface consisting of a data clock
(DCLK), a transmit enable pin (DXMIT), a valid data pin
(DVALID), a serial data output pin (DOUT), and a serial data
input pin (DIN). The DDC112 contains only one A/D converter,
so the conversion process is interleaved between the two
inputs (see Figure 2). The integration and conversion process
is fundamentally independent of the data retrieval process.
Consequently, the CLK frequency and DCLK frequencies
need not be the same. DIN is used when multiple converters
are cascaded. Cascading or
daisy-chaining greatly simplifies
the interconnection and routing of the digital outputs in cases
where a large number of converters are needed. Refer to the
Cascading Multiple Converters section of this data sheet for
more detail.
The conversion rate of the DDC112 is set by a combination of
the integration time (determined by the user) and the speed of
the A/D conversion process. The A/D conversion time is
primarily a function of the system clock (CLK) speed. One
A/D conversion cycle encompasses the conversion of two
signals (one from each input of the DDC112) and reset time
for each of the integrators involved in the two conversions. In
most situations, the A/D conversion time is shorter than the
integration time. If this condition exists, the DDC112 will
operate in the continuous mode. When the DDC112 is in the
continuous mode, the sensor output is continuously integrated
by one of the two sides of each input.
In the event that the A/D conversion takes longer than the
integration time, the DDC112 will switch into a noncontinu-
ous mode. In noncontinuous mode, the A/D converter is not
able to keep pace with the speed of the integration process.
Consequently, the integration process is periodically halted
until the digitizing process catches up. These two basic
modes of operation for the DDC112—continuous and non-
continuous modes—are described in the
Continuous and
Noncontinuous Operational Modes section of this data sheet.
Continuous and Non-Continuous
Operational Modes
The state diagram of the DDC112 is shown in Figure 9. In all,
there are 8 states. Table IV provides a brief explanation of
each of the states.
Int A/Meas B
Cont
5
CONV mbsy
CONV
Int B/Meas A
Cont
4
Ncont
1
Ncont
2
Int A
Cont
3
Ncont
8
Ncont
7
Int B
Cont
6
CONV
mbsy
FIGURE 9. State Diagram.
Four signals are used to control progression around the state
diagram: CONV and mbsy and their complements. The state
machine uses the level as opposed to the edges of CONV to
control the progression. mbsy is an internally-generated
signal not available to the user. It is active whenever a
measurement/reset/auto-zero (m/r/az) cycle is in progress.
STATE
MODE
DESCRIPTION
1
Ncont
Complete m/r/az of side A, then side B (if previous
state is state 4). Initial power-up state when CONV
is initially held HIGH.
2
Ncont
Prepare side A for integration.
3
Cont
Integrate on side A.
4
Cont
Integrate on side B; m/r/az on side A.
5
Cont
Integrate on side A; m/r/az on side B.
6
Cont
Integrate on side B.
7
Ncont
Prepare side B for integration.
8
Ncont
Complete m/r/az of side B, then side A (if previous
state is state 5). Initial power-up state when CONV
is initially held LOW.
TABLE IV. State Descriptions.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DDC112UG4 | 功能描述:模数转换器 - ADC Dual Current Input 20-Bit RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| DDC112UK | 功能描述:模数转换器 - ADC Dual Current Input 20-Bit RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| DDC112UK | 制造商:Texas Instruments 功能描述:DUAL CURRENT INPUT 20 BIT ANALOG/DIGITAL |
| DDC112UK | 制造商:Texas Instruments 功能描述:20BIT ADC DUAL SMD SOIC28 112 |
| DDC112UK/1K | 功能描述:模数转换器 - ADC Dual Current Input 20-Bit RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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