参数资料
型号: DG534ADN-E3
厂商: Vishay Siliconix
文件页数: 1/17页
文件大小: 0K
描述: IC AMP/VIDEO/MUX LP 4/8CH 20PLCC
标准包装: 500
功能: 视频多路复用器
电路: 2 x 2:1
导通状态电阻: 90 欧姆
电压电源: 单/双电源
电压 - 电源,单路/双路(±): 10 V ~ 18 V,±10 V ~ 15 V
电流 - 电源: 600µA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-LCC(J 形引线)
供应商设备封装: 20-PLCC(9x9)
包装: 管件
DG534A/538A
Vishay Siliconix
Document Number: 70069
S-05734—Rev. G, 29-Jan-02
www.vishay.com
1
4-/8-Channel Wideband Video Multiplexers
FEATURES
BENEFITS
APPLICATIONS
D Wide Bandwidth: 500 MHz
D Very Low Crosstalk: –97 dB @ 5 MHz
D On-Board TTL-Compatible Latches with
Readback
D Optional Negative Supply
D Low rDS(on): 45 W
D Single-Ended or Differential Operation
D Latch-up Proof
D Improved System Bandwidth
D Improved Channel Off-Isolation
D Simplified Logic Interfacing
D High-Speed Readback
D Allows Bipolar Signal Swings
D Reduced Insertion Loss
D Allows Differential Signal Switching
D Wideband Signal Routing and
Multiplexing
D Video Switchers
D ATE Systems
D Infrared Imaging
D Ultrasound Imaging
DESCRIPTION
The DG534A is a digitally selectable 4-channel or dual
2-channel multiplexer. The DG538A is an 8-channel or dual
4-channel multiplexer. On-chip TTL-compatible address
decoding logic and latches with data readback are included to
simplify the interface to a microprocessor data bus. The low
on-resistance and low capacitance of the these devices make
them ideal for wideband data multiplexing and video and audio
signal routing in channel selectors and crosspoint arrays. An
optional negative supply pin allows the handling of bipolar
signals without dc biasing.
The DG534A/DG538A are built on a D/CMOS process that
combines n-channel DMOS switching FETs with low-power
CMOS control logic, drivers and latches. The low-capacitance
DMOS FETs are connected in a “T” configuration to achieve
extremely high levels of off isolation. Crosstalk is reduced to
–97 dB at 5 MHz by including a ground line between adjacent
signal paths. An epitaxial layer prevents latch-up.
For more information refer to Vishay Siliconix applications
note AN502.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
GND
NC
DA
DB
V+
V–
SA1
SB1
GND
SA2
SB2
4/2
VL
RS
I/O
Dual-In-Line
Top View
912
WR
EN
10
11
A1
A0
Latches/Drivers
PLCC
14
15
16
17
18
8
7
6
5
4
1
2
319
20
11
10
913
12
Top View
SA1
SB1
GND
SA2
SB2
4/2
VL
RS
NC
1
0
EN
I/O
V+
D
GND
D
V–
Latch/Drivers
A
B
WR
DG534ADN
DG534ADJ
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