
Document Number: 70071
S-71241–Rev. H, 25-Jun-07
www.vishay.com
13
Vishay Siliconix
DG884
APPLICATIONS
A typical switching threshold versus VL is shown in Figure 15.
These devices feature an address readback facility whereby
the last address written to the device may be read by the
system. This allows improved status monitoring and hand
shaking without additional external components.
When the I/O assigns the address output condition, the AX
address pins can sink or source current for logic low and
high, respectively. Note that VL is the logic high output
condition. This point must be respected if VL is varied for
input logic threshold shifting.
Note: Even though these devices are designed to be latchup
resistant, VL must not exceed V+ by more than 0.3 V in
operation or during power supply on/off sequencing.
Layout
The PLCC package pinout is optimized so that large
crosspoint arrays can be easily implemented with a minimum
number of PCB layers (see Figure 16). Crosstalk is
minimized and off-isolation is optimized by having ground
pins located adjacent to each input and output signal pins.
Optimum off-isolation and low crosstalk performance can
only be achieved by the proper use of RF layout techniques:
avoid sockets, use ground planes, avoid ground loops,
bypass the power supplies with high frequency type
capacitors (low ESR, low ESL), use striplines to maintain
transmission line impedance matching.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?70071.
Figure 16. 16 X 8 Expandable Crosspoint Matrix Using DG884
Video
In Bus
Video
In Bus
Video
In Bus
Video
In Bus
Video
Out Bus
Video
Out Bus
Video
Out Bus
Video
Out Bus
Address
Bus
Address
Bus