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| 型号： | DK-DEV-4SE530N |
| 厂商： | Altera |
| 文件页数： | 20/58页 |
| 文件大小： | 0K |
| 描述： | KIT DEV STRATIX IV FPGA 4SE530 |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 1 |
| 系列： | Stratix® IV |
| 类型： | FPGA |
| 适用于相关产品： | EP4SE530 |
| 所含物品： | 板，线缆，CD，DVD，电源 |
| 产品目录页面： | 607 (CN2011-ZH PDF) |
| 其它名称： | 544-2605 |
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4–4
Chapter 4: Development Board Setup
Factory Default Switch Settings
Table 4–1. SW1 Dip Switch Settings (Part 2 of 2)
Switch
Board
Label
Function
Default
Position
Switch 3 has the following options:
3
CLK100_EN
■
When on, the 100 MHz clock is disabled.
Off
■
When off, the 100 MHz clock is enabled.
Switch 4 has the following options:
4
CLK125_EN
■
When on, the 125 MHz clock is disabled.
Off
■
When off, the 125 MHz clock is enabled.
Table 4–2. SW2 Dip Switch Settings
Switch
Board
Label
Function
Default
Position
Switch 1 is a MAX II user-defined switch and has the following options:
1
DIP0
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 2 is a MAX II user-defined switch and has the following options:
2
DIP1
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 3 is a MAX II user-defined switch and has the following options:
3
DIP2
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 4 is a MAX II user-defined switch and has the following options:
4
DIP3
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 5 is a MAX II user-defined switch and has the following options:
5
DIP4
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 6 is a MAX II user-defined switch and has the following options:
6
DIP5
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 7 is a MAX II user-defined switch and has the following options:
7
DIP6
■
When closed, a logic 0 is selected.
Closed
■
When open, a logic 1 is selected.
Switch 8 has the following options:
8
CLK66_SEL
■
When closed, the 66 MHz clock is selected.
Closed
■
When open, the SMA input clock is selected.
Stratix IV E FPGA Development Kit User Guide
June 2011 Altera Corporation
相关PDF资料 |
PDF描述 |
|---|---|
| DK-DEV-4SGX530N | KIT DEVELOPMENT STRATIX IV |
| DK-DEV-5AGXB3N/ES | ARRIA V DEVELOPMENT KIT |
| DK-DEV-5M570ZN | KIT DEV MAX V 5M570Z |
| DK-DEV-5SGXEA7N | KIT DEV STRATIX V FPGA 5SGXEA7 |
| DK-DSP-2S180N | DSP PRO KIT W/SII EP2S180N |
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