参数资料
型号: DK-DEV-4SE530N
厂商: Altera
文件页数: 50/58页
文件大小: 0K
描述: KIT DEV STRATIX IV FPGA 4SE530
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 1
系列: Stratix® IV
类型: FPGA
适用于相关产品: EP4SE530
所含物品: 板,线缆,CD,DVD,电源
产品目录页面: 607 (CN2011-ZH PDF)
其它名称: 544-2605
6–24
Chapter 6: Board Test System
Configuring the FPGA Using the Quartus II Programmer
Calculating Power
The Power Monitor calculates power by measuring two different voltages with the
LT2418 A/D and applying the equation P = V × I to determine the power
consumption. The LT2418 measures the voltage after the appropriate sense resistor
( Vsense ) and the voltage drop across that sense resistor ( Vdif ). The current ( I ) is
calculated by dividing the measured voltage drop across the resistor by the value of
the sense resistor ( I = Vdif / R ). Through substitution, the equation for calculating
power becomes P = V × I = Vsense × ( Vdif / R ) = ( Vsense ) × ( Vdif ) × (1/.003).
You can verify the power numbers shown in the Power Monitor with a digital
multimeter that is capable of measuring microvolts to ensure you have enough
significant digits for an accurate calculation. Measure the voltage on one side of the
resistor (the side opposite the power source) and then measure the voltage on the
other side. The first measurement is Vsense and the difference between the two
measurements is Vdif . Plug the values into the equation to determine the power
consumption.
Configuring the FPGA Using the Quartus II Programmer
You can use the Quartus II Programmer to configure the FPGA with a specific .sof .
Before configuring the FPGA, ensure that the Quartus II Programmer and the
USB-Blaster driver are installed on the host computer, the USB cable is connected to
the FPGA development board, power to the board is on, and no other applications
that use the JTAG chain are running.
To configure the Stratix IV E FPGA, perform the following steps:
1. Start the Quartus II Programmer.
2. Click Add File and select the path to the desired .sof .
3. Turn on the Program/Configure option for the added file.
4. Click Start to download the selected file to the FPGA. Configuration is complete
when the progress bar reaches 100%.
1
Using the Quartus II programmer to configure a device on the board causes other
JTAG-based applications such as the Board Test System and the Power Monitor to
loose their connection to the board. Restart those applications after configuration is
complete.
Stratix IV E FPGA Development Kit User Guide
June 2011 Altera Corporation
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