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参数资料
| 型号： | DK-N2EVAL-3C25N |
| 厂商： | Altera |
| 文件页数： | 24/36页 |
| 文件大小： | 0K |
| 描述： | KIT DEV NIOS II CYCLONE III ED. |
| 产品培训模块： | Cyclone® III FPGA NiosII Embedded Processors Three Reasons to Use FPGA's in Industrial Designs |
| 特色产品： | Nios? II Embedded Evaluation Kit, Cyclone? III Edition |
| 标准包装： | 1 |
| 系列： | Cyclone® III |
| 类型： | FPGA |
| 适用于相关产品： | EP3C25 |
| 所含物品： | 开发板，模块和软件 |
| 产品目录页面： | 606 (CN2011-ZH PDF) |
| 相关产品： | 544-2565-ND - IC CYCLONE III FPGA 25K 324 FBGA 544-2564-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2563-ND - IC CYCLONE III FPGA 80K 484 UBGA 544-2562-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2561-ND - IC CYCLONE III FPGA 80K 484 FBGA 544-2560-ND - IC CYCLONE III FPGA 5K 256 UBGA 544-2559-ND - IC CYCLONE III FPGA 5K 164 MBGA 544-2558-ND - IC CYCLONE III FPGA 5K 256 FBGA 544-2557-ND - IC CYCLONE III FPGA 5K 144 EQFP 544-2556-ND - IC CYCLONE III FPGA 55K 484 UBGA 更多... |
| 其它名称： | 544-2411 DK-N2EVAL-3C25N-OB DK-NIOSEVAL-3C25N NEEK |
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Measuring Power
Table 4–3. LEDs Power State (Resources)
LEDs
Displays
MSB
LSB
State
% of Design Used
Resources
LED4
LED3
00
25 %
01
10
11
50 %
75 %
100 %
The design used for power measurement is a replicated set of randomly
filled ROMs that feed a multiplier block and a shift register that is fed by
a signal that changes every clock cycle. Tables 4–2 and 4–3 show the
power state which represent the percent of the full design used. As
compiled, this full design uses:
■
■
■
■
■
■
■
■
Logic elements: 22,493/24,624 (91%)
Combinational functions: 1,961/24,624 (8%)
Dedicated logic registers: 21,133/24,624 (86%)
Total registers: 21,133
Total pins: 73/216 (34%)
Total memory bits: 524,288/608,256 (86%)
Embedded Multiplier 9-bit elements: 128/132 (97 %)
Total PLLs: 1/4 (25%)
Measuring
Power
The example design is located in
< kit install > \examples\cycloneIII_3c25_start_power_demo . Configure
the FPGA with the .sof found in the directory.
1
The input clock ( i_clk PIN_B9) is the 50-MHz oscillator on the
board, which generates the input clock for the reference design
through a PLL
f
For more information on configuring the FPGA, refer to “Configuring
the FPGA Using the Quartus II Programmer” on page 2–3 .
Current sense resistors (0.010 ? ± 1%) are installed at locations JP6 (FPGA
core power) and JP3 (FPGA I/O power + other device I/O power). With
a digital multimeter set to mV measurement range, the resistor at location
JP6 measures the core power. The resistor at location JP3 measures the
I/O power. To measure the current being used in various configurations,
use the following steps:
4–2
Altera Corporation
Cyclone III FPGA Starter Kit User Guide
July 2010
相关PDF资料 |
PDF描述 |
|---|---|
| DK-NIOS-2C35N | NIOS II KIT W/CYCLONE II EP2C35N |
| DK-NIOS-2S60N | NIOS II KIT W/STRATIX II EP2S60N |
| DK-PCI-2C35N | PCI KIT W/CYCLONE II EP2C35N |
| DK-PCIE-2SGX90N | PCIE KIT W/S II GX EP2SGX90N |
| DK-SI-2SGX90N | SI KIT W/SII GX EP2SGX90N |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DK-N2EVAL-3C25N/QP | 制造商:Altera Corporation 功能描述: |
| DK-N2EVAL-3C25N-OJ | 制造商:Altera 功能描述:DK-N2EVAL-3C25N-OJ |
| DK-N55224 | 制造商:Brother 功能描述: |
| DKN7900P-4-AA-1 | 制造商:DEUTSCH FAST / HUCK 功能描述: |
| DKNIL12VF | 制造商:PANASONIC 制造商全称:Panasonic Semiconductor 功能描述:10 A MINIATURE POWER RELAY |
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