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| 型号： | DMA-MC-XM-N3 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 20/28页 |
| 文件大小： | 0K |
| 描述： | IP CORE MCDMA CTLR XP LATTICEXP |
| 标准包装： | 1 |
| 系列： | * |
| 其它名称： | DMAMCXMN3 |
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Lattice Semiconductor
Multi-Channel DMA Controller User’s Guide
Table 11. Status Register: Access One Bit – 8237 Mode
Bit
0
1
2
3
4
5
6
7
Table 12. Non-8237 Internal Registers
Description
Channel 0 terminal count
Channel 1 terminal count
Channel 2 terminal count
Channel 3 terminal count
Channel 0 request
Channel 1 request
Channel 2 request
Channel 3 request
8,16,32 or 64
Name
Source Address Register
Word Count Register
Destination Address Register
Command Register
Temporary Register
Mode Register
Channel Control Register
Size in Bits
16, 24 or 32 1
8, 16, 24 or 32 2
16, 24 or 32 1
4
3
8
3
Number of Registers
N 4
N
N
1
1
N
N
1.
2.
3.
4.
Based on the width of the address bus selected
Based on the width of the word count register selected
Based on the width of the data bus selected
N = Number of channels selected
Source Address Register
This register is only available in the non-8237 mode. Each channel has a Source Address Register whose width
matches with the address bus width. This register stores the value of the source or memory address used during
DMA transfers. The address is automatically incremented or decremented by 1, 2, or 4 after each transfer, depend-
ing on the respective data bus width of 8, 16 or 32 bits. This register has to be written in consecutive cycles after
clearing the byte pointer. The number of cycles taken to access this register depends on the size of the address
bus. During a DMA transfer between an I/O location and memory, this register holds the address of the memory
location. During a memory-to-memory transfer, this register stores the address of the location that is read from.
The user must always program the register with the address that is aligned with the width of the data bus.
Destination Address Register
This register is only available in the non-8237 mode. Each channel has a Destination Address Register whose
width matches with the address bus width. The address is automatically incremented or decremented by 1, 2, or 4
after each transfer depending on the respective data bus width of 8, 16 or 32 bits. This register has to be written in
consecutive cycles after clearing the byte pointer. The number of cycles taken to access this register depends on
the size of the address bus. During memory-to-memory transfers, this register stores the address of the memory
location that is written into. This register is not used during DMA transfers between memory and I/O. The user must
always program the register with the address that is aligned with the width of the data bus.
Word Count Register
This register is only available in non-8237 mode, and its width is con?gurable. This register determines the number
of transfers to be performed. The actual number of transfers is one more than the value programmed into this reg-
ister. The current word count is decremented after each transfer. When the value in the register goes from zero to
0xFFFF, a Terminal Count ( eopout_n ) signal is generated. At the end of a DMA transfer, this register has a value
of 0xFFFF if auto-initialization is not enabled for the channel.
20
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相关代理商/技术参数 |
参数描述 |
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| DMA-MC-XP-N2 | 功能描述:数字信号处理器和控制器 - DSP, DSC DMA Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DM-A-PP | 制造商:DDK 制造商全称:DDK Ltd. 功能描述:Conversion Connector |
| DMA-SG-E3-U1 | 功能描述:开发软件 DMA Scatter/Gather RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| DMA-SG-E3-UT1 | 功能描述:开发软件 DMA SCATTER/GATHER USER CONFIGURABLE RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
| DMA-SG-P2-U1 | 功能描述:开发软件 DMA Scatter/Gather RoHS:否 制造商:Atollic Inc. 产品:Compilers/Debuggers 用于:ARM7, ARM9, Cortex-A, Cortex-M, Cortex-R Processors |
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