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参数资料
| 型号： | SFCF8192H2BU2TO-I-QT-517-STD |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 12/102页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 8GB |
| 标准包装： | 1 |
| 系列： | C-440 |
| 存储容量： | 8GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1092 |
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Pin Num
PC Card Memory Mode
PC Card I/O Mode
True IDE Mode
(4)
Signal
Name
Pin
Type
In, Out
Type
Signal
Name
Pin
Type
In, Out
Type
Signal
Name
Pin
Type
In, Out
Type
D15
D15
D15
31
(1)
I/O
I1Z,OZ3
(1)
I/O
I1Z,OZ3
(1)
I/O
I1Z,OZ3
-CE2
-CE2
32
(1)
I
I3U
(1)
I
I3U
-CS1
(1)
I
I3Z
33
-VS1
O
Ground
-VS1
O
Ground
-VS1
O
Ground
-IORD
(7)
34
-IORD
I
I3U
-IORD
I
I3U
HSTROBE
(8)
I
I3Z
-HDMARDY
(9)
-IOWR
STOP
35
-IOWR
I
I3U
-IOWR
I
I3U
(7)
(8)(9)
I
I3Z
36
-WE
I
I3U
-WE
I
I3U
-WE
(3)
I
I3U
37
READY
O
OT1
-IREQ
O
OT1
INTRQ
O
OZ1
38
Vcc
Power
Vcc
Power
Vcc
Power
-CSEL
-CSEL
39
40
41
(5)
-VS2
RESET
I
O
I
I2Z
OPEN
I2U
(5)
-VS2
RESET
I
O
I
I2Z
OPEN
I2U
-CSEL
-VS2
-RESET
I
O
I
I2U
OPEN
I2U
IORDY
(7)
42
-WAIT
O
OT1
-WAIT
O
OT1
-DDMARDY
(8)
O
ON1
DSTROBE
(9)
43
-INPACK
O
OT1
-INPACK
O
OT1
DMARQ
O
OZ1
44
-REG
I
I3U
-REG
I
I3U
-DMACK
(6)
I
I3U
45
46
BVD2
BVD1
I/O
I/O
I1U,OT1
I1U,OT1
-SPKR
-STSCHG
I/O
I/O
I1U,OT1
I1U,OT1
-DASP
-PDIAG
I/O
I/O
I1U,ON1
I1U,ON1
47
D8
(1)
I/O
I1Z,OZ3
D8
(1)
I/O
I1Z,OZ3
D8
(1)
I/O
I1Z,OZ3
48
D9
(1)
I/O
I1Z,OZ3
D9
(1)
I/O
I1Z,OZ3
D9
(1)
I/O
I1Z,OZ3
D10
D10
D10
49
(1)
I/O
I1Z,OZ3
(1)
I/O
I1Z,OZ3
(1)
I/O
I1Z,OZ3
50
GND
Ground
GND
Ground
GND
Ground
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
These signals are required only for 16 bit accesses and not required when installed in 8 bit systems.
Devices should allow for 3-state signals not to consume current.
The signal should be grounded by the host.
The signal should be tied to VCC by the host.
The mode is required for CompactFlash TM Storage Cards.
The – CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled up on the card
in these modes, it should not be left floating by the host in PC Card modes. In these modes, the pin
should be connected by the host to PC Card A25 or grounded by the host.
If DMA operations are not used, the signal must be held high or tied to VCC by the host, also for read
registers.
Signal usage in True IDE Mode except when Ultra DMA mode protocol is active.
Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Write is active.
Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Read is active. The signal should be
grounded by the host.
In PC-Card mode, the IOIS16 signal does not work as fully specified. If a host uses this signal, this may
result in 16 bit accesses being changed to two 8 bit accesses. Depending on the address, this may result
in an incompatibility with the host controller.
In PC-Card mode (memory and I/O), 16 bit ATA register file accesses (i.e. both -CE1 and -CE2 asserted) do
not work as fully specified if A0 is high.
If you have host-card incompatibilities please contact Swissbit.
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev100.doc
Page 12 of 102
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