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| 型号： | SFCF8192H2BU2TO-I-QT-517-STD |
| 厂商： | Swissbit NA Inc |
| 文件页数： | 49/102页 |
| 文件大小： | 0K |
| 描述： | FLASH SLC UDMA/MDMA/PIO 8GB |
| 标准包装： | 1 |
| 系列： | C-440 |
| 存储容量： | 8GB |
| 存储器类型： | CompactFlash? |
| 其它名称： | 1052-1092 |
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Table 43: Memory Mapped Decoding
- REG
A10 A9 to A4
A3
A2
A1
A0
Offset
- OE=0
- WE=0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
X
X
0
0
0
0
1
1
1
1
0
0
1
1
1
X
X
0
0
1
1
0
0
1
1
0
0
0
1
1
X
X
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Dh
Eh
Fh
8h
9h
Even Data Register
Error Register
Sector Count Register
Sector Number Register
Cylinder Low Register
Cylinder High Register
Select Card/Head Register
Status Register
Dup. Even Data Register
Dup. Odd Data Register
Dup. Error Register
Alternate Status Register
Drive Address Register
Even Data Register
Odd Data Register
Even Data Register
Feature Register
Sector Count Register
Sector Number Register
Cylinder Low Register
Cylinder High Register
Select Card/Head Register
Command Register
Dup. Even Data Register
Dup. Odd Data Register
Dup. Feature Register
Device Control Register
Reserved
Even Data Register
Odd Data Register
8.3 Contiguous I/O Mapped Addressing
When the system decodes a contiguous block of I/O registers to select the Card, the registers are accessed in the
Address A0 must be low for all word accesses. As for the Memory Mapped Addressing, register 0 is accessed with –
CE1 Low and – CE2 Low (A0 must be 0) as a Word register on the combined Odd and Even Data Bus (D15 to D0). This
register may also be accessed with – CE1 Low and – CE2 High, by a pair of Byte accesses to offset 0. The address
space of this Word register overlaps the address space of the Error and Feature Byte-wide registers at offset 1.
When accessed twice as Byte register with – CE1 Low, the first Byte is the even Byte of the Word and the second is
the odd Byte. A Byte access to register 0 with – CE1 High and – CE2 Low accesses the error (read) or feature (write)
register.
Registers at offset 8, 9 and D are non-overlapping duplicates of the registers at offset 0 and 1. Register 8 is
equivalent to register 0, while register 9 accesses the odd Byte. Therefore, if the registers are Byte accessed in the
order 9 then 8 the data will be transferred odd Byte then even Byte. Repeated Byte accesses to register 8 or 0 will
access consecutive (even than odd) Bytes from the data buffer. Repeated Word accesses to register 8, 9 or 0 will
access consecutive Words from the data buffer, however repeated Byte accesses to register 9 are not supported.
Repeated alternating Byte accesses to registers 8 then 9 will access consecutive (even then odd) Bytes from the
data buffer.
Table 44: Contiguous I/O Decoding
- REG
0
0
0
0
0
0
0
0
0
0
0
0
0
A10 to A4
X
X
X
X
X
X
X
X
X
X
X
X
X
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
A2
0
0
0
0
1
1
1
1
0
0
1
1
1
A1
0
0
1
1
0
0
1
1
0
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
1
0
1
Offset
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Dh
Eh
Fh
- IORD=0
Even Data Register
Error Register
Sector Count Register
Sector Number Register
Cylinder Low Register
Cylinder High Register
Select Card/Head Register
Status Register
Dup. Even Data Register
Dup. Odd Data Register
Dup. Error Register
Alternate Status Register
Drive Address Register
- IOWR=0
Even Data Register
Feature Register
Sector Count Register
Sector Number Register
Cylinder Low Register
Cylinder High Register
Select Card/Head Register
Command Register
Dup. Even Data Register
Dup. Odd Data Register
Dup. Feature Register
Device Control Register
Reserved
Swissbit AG
Industriestrasse 4
Swissbit reserves the right to change products or specifications without notice.
Revision: 1.00
CH-9552 Bronschhofen
Switzerland
www.swissbit.com
industrial@swissbit.com
C-440_data_sheet_CF-HxBU_Rev100.doc
Page 49 of 102
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