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参数资料
| 型号： | DP83848YB-EVK/NOPB |
| 厂商： | National Semiconductor |
| 文件页数： | 41/86页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD PHYTER EXTREME TEMP |
| 标准包装： | 1 |
| 主要目的： | 接口，以太网 |
| 已用 IC / 零件： | DP83848YB |
| 已供物品： | 板 |
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DP
83
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Y
B
The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83848YB. The Identifier consists of a
concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num-
ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended
to support network management. National's IEEE assigned OUI is 080017h.
7.1.3 PHY Identifier Register #1 (PHYIDR1)
7.1.4 PHY Identifier Register #2 (PHYIDR2)
7.1.5 Auto-Negotiation Advertisement Register (ANAR)
This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Nego-
tiation.
Table 14. PHY Identifier Register #1 (PHYIDR1), address 0x02
Bit
Bit Name
Default
Description
15:0
OUI_MSB
<0010 0000 0000
0000>, RO/P
OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are
stored in bits 15 to 0 of this register. The most significant two bits
of the OUI are ignored (the IEEE standard refers to these as bits 1
and 2).
Table 15. PHY Identifier Register #2 (PHYIDR2), address 0x03
Bit
Bit Name
Default
Description
15:10
OUI_LSB
<0101 11>, RO/P OUI Least Significant Bits:
Bits 19 to 24 of the OUI (080017h) are mapped from bits 15 to 10
of this register respectively.
9:4
VNDR_MDL
<00 1001>, RO/P Vendor Model Number:
The six bits of vendor model number are mapped from bits 9 to 4
(most significant bit to bit 9).
3:0
MDL_REV
<0000>, RO/P
Model Revision Number:
Four bits of the vendor model revision number are mapped from
bits 3 to 0 (most significant bit to bit 3). This field will be incremented
for all major device changes.
Table 16. Negotiation Advertisement Register (ANAR), address 0x04
Bit
Bit Name
Default
Description
15
NP
0, RW
Next Page Indication:
0 = Next Page Transfer not desired.
1 = Next Page Transfer desired.
14
RESERVED
0, RO/P
RESERVED by IEEE: Writes ignored, Read as 0.
13
RF
0, RW
Remote Fault:
1 = Advertises that this device has detected a Remote Fault.
0 = No Remote Fault detected.
12
RESERVED
0, RW
RESERVED for Future IEEE use: Write as 0, Read as 0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DP83848YBX/NOPB | 功能描述:以太网 IC RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| DP83849C | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PHYTER? DUAL Commercial Temperature Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver |
| DP83849C_08 | 制造商:NSC 制造商全称:National Semiconductor 功能描述:PHYTER? DUAL Commercial Temperature Dual Port 10/100 Mb/s Ethernet Physical Layer Transceiver |
| DP83849CVS | 功能描述:以太网 IC RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| DP83849CVS | 制造商:Texas Instruments 功能描述:TRANSCEIVER, ENET PHYTER, DUAL, 80TQFP 制造商:Texas Instruments 功能描述:TRANSCEIVER, ENET PHYTER, DUAL, 80TQFP; Data Rate:100Mbps; Ethernet Type:IEEE 802.3u; Supply Voltage Min:3V; Supply Voltage Max:3.6V; Digital IC Case Style:TQFP; No. of Pins:80; Interface Type:MII, RMII, Serial; Operating Temperature;RoHS Compliant: Yes |
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