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参数资料
| 型号： | DP83959AVUL |
| 英文描述： | LAN Hub Controller |
| 中文描述： | 局域网集线器控制器 |
| 文件页数： | 4/24页 |
| 文件大小： | 240K |
| 代理商： | DP83959AVUL |
50 Functional Description (Continued)
53 CPU INTERFACE
This interface allows the CPU to read and write to all of the
DP83957’s registers and to indirectly access the Port attri-
butes stored in the SRAM (via the DP83957) All read and
write accesses are byte wide The DP83857 operates as a
slave device and requires a minimum amount of glue logic
to interface with the CPU
All timing requirements as specified in Section 80 (AC Tim-
ing Conditions) must be satisfied for proper operation
The CPU interface consists of a multiplexed AddressData
bus (AD 70 ) Chip Select (CS) Read enable (RD) Write
enable (WR) Address Latch Enable (ALE) and Interrupt
(INT) signals
531 Register Read Operation
A read to one of the DP83957 registers is initiated by the
CPU logic asserting CS The address (of the desired regis-
ter) is driven onto the AD 70 bus by the CPU and must be
stable before the falling edge of ALE After the T5 time has
elapsed the RD signal can be asserted which switches the
direction of the AD 70 bus (to output)
The data driven out onto the AD 70 bus by the DP83957
will not be valid until the T7 time has elapsed At this point
the AD bus will display the contents of the desired register
(refer to Section 81 CPU Read Timing Diagrams)
532 Register Write Operation
A write to one of the DP83957 registers is initiated by the
CPU logic asserting CS The address (of the desired regis-
ter) is driven onto the AD 70 bus by the CPU and must be
stable before the falling edge of ALE The data that is writ-
ten to the DP83957 must be stable before the de-assertion
(rising edge) of WR (refer to Section 82 CPU Write Timing
Diagrams)
533 Interrupts
The INT is an active low signal driven by the DP83957 to
indicate that an interrupt has been generated
The INT signal is shared between the maskable status inter-
rupts and the error reporting interrupts
The source of the interrupt can be determined by reading
the Interrupt Status Register (refer to Section 67 for the bit
definition)
The CPU clears the generated interrupt by writing a ‘‘1’’ to
that bit in the Interrupt Status Register Writing a ‘‘0’’ to a bit
has no effect
The following events can cause the DP83957 to drive the
INT pin low
Source Address Mismatch (SAM)
Management Bus Error
(SFD
ERR or k56 bits)
SRAM Write complete (WR
COM)
SRAM Read Complete (RD
COM)
Invalid Port Number Received (IPN)
Attribute Overflow (OVFL)
Any of the above events can be masked by setting the cor-
responding bit in the Interrupt Mask Register (refer to Sec-
tion 65 for the bit definition)
The INT output pin can be disabled (TRI-STATE ) by set-
ting the INT bit D6 in Configuration Register 1
54 REGISTERS
The DP83957 has 18 registers that are used to control the
operation of the DP83957 and obtain the attribute informa-
tion stored in the SRAM The following section provides a
brief description of these registers Refer to Section 60
DP83957 Register Description for a more detailed explana-
tion
Configuration Registers 1 – 3
These registers are used to control and configure the
DP83957
Interrupt Mask Register
This register specifies the events that can cause the INT pin
to be driven active by the DP83957
Interrupt Status Register
This register specifies the source (event) that caused the
INT pin to be driven by the DP83957 The bit(s) can be
cleared by writing a ‘‘1’’
Read Data Registers 1 – 6
When the CPU requests a SRAM read of an attribute the
DP83957 transfers the data obtained from the SRAM into
these holding registers
Access Registers 1 – 2
Access Registers 1 and 2 specify the address for the SRAM
read and write operation The address consists of a page
(DP839502 ID and Port ID) and offset (Port attribute)
Write Data Byte Register
This register contains the value to be written to a SRAM
location during a write operation or during a SRAM fill oper-
ation
DP83950 or DP83952 ID Registers 1 – 2
These
registers
contain
the
DP839502
ID
of
the
DP839502’s that are dedicated to this DP83957
Overflow Status Registers 1 – 2
Overflow Status Registers 1 and 2 contain indirectly the
DP83950 ID the actual Port ID and the attribute whose
counter has rolled over from 0xFF to 0x00
12
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