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参数资料
| 型号： | DR7003-DK |
| 厂商： | RFM |
| 文件页数： | 3/7页 |
| 文件大小： | 0K |
| 描述： | 3G DEVELOPMENT KIT 303.825 MHZ |
| 标准包装： | 1 |
| 类型： | 收发器 |
| 频率： | 303.825MHz |
| 适用于相关产品： | DR7003 |
| 已供物品： | 2 个板，2 根天线，线缆，CD |
| 其它名称： | 583-1047 |
Pin Descriptions
Pin
1,4,20
19
Name
GND
VCC
In/Out
-
-
GND is the ground pin.
VCC is a positive supply voltage pin.
Description
This pin is the peak detector output. A 0.022uF capacitor to ground (C5) sets the peak detector attack and
decay times, which have a fixed 1:1000 ratio. For most applications, these time constants should be coordi-
nated with the base-band time constant. For a given base-band capacitor C BBO , the capacitor value C PKD is:
C PKD = 2.0* C BBO , where C BBO and C PKD are in pF
2
PKDET
Out
A ±10% ceramic capacitor should be used at this pin. This time constant will vary between t PKA and 1.5* t PKA
with variations in supply voltage, temperature, etc. The capacitor is driven from a 200 ohm “attack” source,
and decays through a 200 K load. The peak detector is used to drive the “dB-below-peak” data slicer and the
AGC release function. The peak detector capacitor is discharged in the receiver power-down (sleep) mode
and in the transmit modes. See the description of Pin 3 below for further information. A 0.022uF capacitor is
installed for operation at 4.8kbps.
This pin is connected directly to the transceiver BBOUT pin. This pin drives the CMPIN pin through a coupling
capacitor, C BBO = 0.01uF (C4), for internal data slicer operation at 4.8kbps.
C BBO = 11.2*SP MAX , where SP MAX is the maximum signal pulse width in μs and C BBO is in pF
The nominal output impedance of this pin is 1 K.The BBOUT signal changes about 10 mV/dB, with a peak-to-
peak signal level of up to 450 mV. The signal at BBOUT is riding on a 1.5 Vdc value that varies somewhat
3
BBOUT
Out
with supply voltage and temperature, so it should be coupled through a capacitor to an external load. When
an external data recovery process is used with AGC, BBOUT must be coupled to the external data recovery
process and CMPIN by separate series coupling capacitors. The output impedance of this pin becomes very
high in sleep mode, preserving the charge on the coupling capacitor.
The value of C3 on the circuit board has been chosen to match typical data encoding schemes at 4.8 kbps. If
C4 is modified to support higher data rates and/or different data encoding schemes and PK DET is being
used, make the value of the peak detector capacitor C5 about 2x the value of C BBO .
RXDATA is the receiver data output pin. It is a CMOS output. The signal on this pin can come from one of two
sources. The default source is directly from the output of the data slicer circuit. The alternate source is from
5
RXDATA
Out
the radio’s internal data and clock recovery circuit. When the internal data and clock recovery circuit is used,
the signal on RXDATA is switched from the output of the data slicer to the output of the data and clock recov-
ery circuit when a packet start symbol is detected. Each recovered data bit is then output on the rising edge of
a RXDCLK pulse (Pin 16), and is stable for reading on the falling edge of the RXDCLK pulse.
The transmitter RF output voltage is proportional to the input current to this pin. A resistor in series with the
TXMOD input is normally used to adjust the peak transmitter output. Full transmitter power (10 mW) requires
about 235 μA of drive current. The transmitter output power P O for a 3 Vdc supply voltage is approximately:
PO = 180*(I TXM ) 2 , where PO is in mW and the modulation current I TXM is in mA
6
TXMOD
In
The practical power control range is 10 to -50 dBm. A ±5% TXMOD resistor value is recommended. Internally,
this pin is connected to the base of a bipolar transistor with a small emitter resistor. The voltage at the
TXMOD input pin is about 0.85 volt with 235 uA of drive current. This pin accepts analog modulation and can
be driven with either logic level data pulses (unshaped) or shaped data pulses.
A series 9.1 kilohm resistor is installed to provide +10dBm average output power with a +3Vdc input.
This pin is the receiver low-pass filter bandwidth adjust. The filter bandwidth is set by a resistor R LPF (R4)
between this pin and ground. The resistor value can range from 510 K to 3 K, providing a filter 3 dB bandwidth
f LPF from 5 to 600 kHz. The resistor value is determined by:
7
LPFADJ
In
R LPF = (0.0006*f LPF ) -1.069 where R LPF is in kilohms, and f LPF is in kHz
A ±5% resistor should be used to set the filter bandwidth. This will provide a 3 dB filter bandwidth between
f LPF and 1.3* f LPF with variations in supply voltage, temperature, etc. The filter provides a three-pole, 0.05
degree equiripple phase response. A 470 kilohm resistor to GND is installed to provide a 3dB filter band-
width of 5.275kHz. Connect an external ±1%, 243kilohm resistor to GND for 19.2kbps operation.
8
TX/RX
In
Logic Input (CMOS compatible). This pin, in 3G mode, selects the operation of the TR7003 . Pull this pin
‘High’ for Transmit Mode. Pull this pin ‘Low’ for Receive mode. Do not allow this pin to float.
www.RFM.com E-mail: info@rfm.com
?2008 by RF Monolithics, Inc.
Page 3 of 7
DR7003 - 4/8/08
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