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参数资料
| 型号： | DS1052Z-100+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 14/14页 |
| 文件大小： | 0K |
| 描述： | IC PROG PWM 5BIT 100KHZ 8-SOIC |
| 标准包装： | 100 |
| 类型： | 脉宽调制器（PWM） |
| PLL： | 无 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 100kHz |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | * |
| 包装： | 管件 |
DS1052
9 of 14
NOTES:
1.
All voltages are referenced to ground.
2.
ICC specified with outputs open.
3.
I/O pins of fast mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
4.
Address Inputs, A0, A1, and A2, should be tied to either VCC or GND depending on the desired
address selections.
5.
ISTBY specified for VCC between 3.0V and 5.0V, control port logic pins are driven to the appropriate
logic levels.
6.
A fast mode device can be used in a standard mode system, but the requirement
tSU:DAT > 250ns must then be met. This will automatically be the case if the device does not stretch
the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250=1250ns before the SCL
line is released.
7.
After this period, the first clock pulse is generated.
8.
The maximum tSU:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
9.
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
VIH MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
10. CB – total capacitance of one bus line in picofarads, timing referenced to (0.9)(VCC) and (0.1)(VCC).
11. A PWM output duty cycle change will occur with 2 periods of the output frequency when a change is
initiated.
12. The absolute frequency output of the PWM can be expected to fall within a
±20% range from the
nominal specified value of the device.
13. The DS1052 is a 5-bit PWM. The output duty cycles of the device range from 0% to 100% in step
sizes of 3.125%. The “Set PWM Duty Cycle 100%” allows the PWM output to be set to full-on.
14. Absolute Linearity is used to compare measured duty cycle against expected duty cycle as
determined by the DAC setting. The DS1052 is specified to provide an absolute linearity of
±0.5
LSB.
15. Relative Linearity is used to determine the change in duty cycle between adjacent or successive duty
cycle settings. The DS1052 is specified to provide a relative linearity specification of
±0.25 LSB.
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相关代理商/技术参数 |
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|---|---|
| DS1052Z-100+ | 功能描述:电压模式 PWM 控制器 RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| DS10-56B | 制造商:TRANSMISSION DEVELOPMENTS 功能描述:MOULDED SPUR GEAR 1.0, 56 |
| DS-105-C | 制造商:Power Dynamics Inc 功能描述: |
| DS-105TR | 制造商:OPTICOMM 制造商全称:OPTICOMM 功能描述:10BaseT Ethernet Transceiver |
| DS106 | 制造商:Cooper Hand Tools / Weller 功能描述: |
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