参数资料
型号: DS1077LU-66
厂商: Maxim Integrated Products
文件页数: 19/21页
文件大小: 0K
描述: IC ECONOSCILLATOR 66.7MHZ 8-USOP
应用说明: DS1077L Application Notes
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
系列: EconOscillator™
类型: 振荡器,固定频率(双路)
频率: 8.13kHz ~ 66.7MHz
电源电压: 2.7 V ~ 3.6 V
电流 - 电源: 30mA
工作温度: -40°C ~ 85°C
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
包装: 管件
供应商设备封装: 8-uMAX
安装类型: 表面贴装
DS1077L
7 of 21
TABLE 5
BIT VALUE
DIVISOR (N)
0 000 000 000
*
2
0 0 00 0 00 001
3
1 111 111 111
1025
*Default Condition
BUS WORD
NAME
WC
A2
A1
A0
Factory Default
0*
0
*These bits are reserved and must be set to zero.
A0, A1, A2
(Default Setting = 000)
These are the device select bits that determine the address of the device.
WC
(Default Setting WC = 0)
This bit determines when/if the EEPROM is written to after register contents have been changed.
If WC = 0, the EEPROM is automatically written after a write register command.
If WC = 1, the EEPROM is only written when the WRITE command is issued.
Regardless of the value of the WC bit, when the BUS register (A0, A1, A2) is written, the current value in
all registers (DIV, MUX, and BUS) are immediately written to the EEPROM.
2-WIRE SERIAL DATA BUS
The DS1077L supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device receiving data as a receiver. The device that controls
the message is called a “master.” The devices that are controlled by the master are “slaves.” The bus must
be controlled by a master device that generates the serial clock (SCL), controls the bus access, and
generates the START and STOP conditions. The DS1077L operates as a slave on the 2-wire bus.
Connections to the bus are made via the open-drain I/O lines, SDA and SCL. A pullup resistor (5k) is
connected to SDA.
The following bus protocol has been defined (see Figure 2):
§ Data transfer may be initiated only when the bus is not busy.
§ During data transfer, the data line must remain stable whenever the clock line is high. Changes in
the data line while the clock line is high will be interpreted as control signals.
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