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参数资料
| 型号： | DS1124U-25+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/10页 |
| 文件大小： | 0K |
| 描述： | IC DELAY LINE 256TAP 10-USOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 3,000 |
| 标片/步级数： | 256 |
| 功能： | 可编程 |
| 延迟到第一抽头： | 20ns |
| 接头增量： | 0.25ns |
| 可用的总延迟： | 83.75ns |
| 独立延迟数： | 1 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-µMAX |
| 包装： | 带卷 (TR) |
DS1124
5.0V 8-Bit Programmable
Timing Element
_______________________________________________________________________________________
3
Note 1: All voltages are referenced to ground.
Note 2: Measured from rising edge of the input to the rising edge of the output. The programmed delay, tD, can be programmed
with values from 0 to 255. See Figure 1.
Note 3: See the
Integral Nonlinearity section and Figure 5.
Note 4: This is the minimum allowable interval between transitions on the input to ensure accurate device operation. This parameter
can be violated but timing accuracy may be impaired and ultimately very narrow pulse widths will result in no output from
the device. See Figure 1.
Note 5: When a 50% duty cycle input clock is used, this defines the highest usable clock frequency. When asymmetrical clock
inputs are used, the maximum usable clock frequency must be reduced to conform to the minimum input pulse-width
requirement. See Figure 1.
Note 6: Faster rise and fall times give the greatest accuracy in measured delay. Slow edges (outside the specification maximum)
can result in erratic operations.
AC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +4.75V to +5.25V, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
E to Delay Valid
tEDV
50
μs
E to Delay Invalid
tEDX
0
ns
Power-Up Time
tPU
100
ms
Delay Step Size
tSTEP
TA = +25°C
-0.75
+0.25
+1
ns
Step 0 Delay
tD0
(Note 2)
17
20
23
ns
Step 0 Delay Initial Accuracy
VCC = 5V, TA = +25°C
-0.6
+0.6
ns
Step 0 Voltage Variation
-0.4
+0.4
ns
Step 0 Temperature Variation
0°C to +70°C
-1
+1
ns
Step 0 Temperature Variation
-40°C to +85°C
-1
+1
ns
Step 255 Delay
tD255
(Note 2)
77
83.75
88
ns
Step 255 Delay Initial Accuracy
VCC = 5V, TA = +25°C
-0.6
+0.6
ns
Step 255 Voltage Variation
-0.4
+0.4
ns
Step 255 Temperature Variation
0°C to +70°C
-3
+3
ns
Step 255 Temperature Variation
-40°C to +85°C
-5
+5
ns
Integral Nonlinearity
(Deviation from Straight Line)
tERR
VCC = 5V, TA = +25°C (Note 3)
-2
0
+2
ns
Minimum Input Pulse Width
tWI
(Note 4)
40
ns
Minimum Input Period
tPER
(Note 5)
80
ns
Input Rise and Fall Times
tR, tF
(Note 6)
0
1
μs
tD0
tD
tWI
IN
OUT
tWI
tD
IN
TIMING REFERENCED TO 1.5V.
OUT
DS1124
Figure 1. Delay Timing Diagram
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