参数资料
型号: DS1238
厂商: DALLAS SEMICONDUCTOR
元件分类: 电源管理
英文描述: MicroManager(微管理器芯片)
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP16
封装: 0.300 INCH, DIP-16
文件页数: 4/13页
文件大小: 167K
代理商: DS1238
DS1238
022698 4/13
WATCHDOG TIMER
The DS1238 provides a watchdog timer function which
forces the WDS, RST, and RST signals to the active
state when the strobe input (ST) is not stimulated for a
predetermined time period. This time period is de-
scribed below in Table 1. The watchdog timeout period
begins as soon as RST and RST are inactive. If a
high-to-low transition occurs at the ST input prior to time
out, the watchdog timer is reset and begins to time out
again. The ST input timing is shown in Figure 2. In order
to guarantee that the watchdog timer does not timeout,
a high-to-low transition on ST must occur at or less than
the minimum timeout of the watchdog as described in
the AC Electrical Characteristics. If the watchdog timer
is allowed to time out, the WDS, RST, and RST outputs
are driven to the active state. WDS is a latched signal
which indicates the watchdog status, and is activated as
soon as the watchdog timer completes a full period as
outlined in Table 1. The WDS pin will remain low until
one of three operations occurs. The first is to strobe the
ST pin with a falling edge, which will both set the WDS as
well as the watchdog timer count. The second is to leave
the ST pin open, which disables the watchdog. Lastly,
the WDS pin is active low whenever V
CC
falls below
V
CCTP
and activates the RVT signal. The ST input can
be derived from microprocessor address, data, or con-
trol signals, as well as microcontroller port pins. Under
normal operating conditions, these signals would rou-
tinely reset the watchdog timer prior to time out. The
watchdog is disabled by leaving the ST input open, or as
soon as V
CC
falls to V
CCTP
.
NON–MASKABLE INTERRUPT
The DS1238 generates a non-maskable interrupt (NMI)
for early warning of a power failure to the microproces-
sor. A precision comparator monitors the voltage level at
the IN pin relative to an on-chip reference generated by
an internal band gap. The IN pin is a high impedance in-
put allowing for a user-defined sense point. An external
resistor voltage divider network (Figure 5) is used to in-
terface with high voltage signals. This sense point may
be derived from the regulated 5-volt supply, or from a
higher DC voltage level closer to the main system power
input. Since the IN trip point V
TP
is 1.27 volts, the proper
values for R1 and R2 can be determined by the equation
as shown in Figure 5. Proper operation of the DS1238
requires that the voltage at the IN pin be limited to V
IH
.
Therefore, the maximum allowable voltage at the supply
being monitored (V
MAX
) can also be derived as shown
in Figure 5. A simple approach to solving this equation is
to select a value for R2 of high enough value to keep
power consumption low, and solve for R1. The flexibility
of the IN input pin allows for detection of power loss at
the earliest point in a power supply system, maximizing
the amount of time for microprocessor shut-down be-
tween NMI and RST or RST.
When the supply being monitored decays to the voltage
sense point, the DS1238 will force the NMI output to an
active state. Noise is removed from the NMI power fail
detection circuitry using built-in time domain hysteresis.
That is, the monitored supply is sampled periodically at
a rate determined by an internal ring oscillator running at
approximately 30 KHz (33
μ
s/cycle). Three consecutive
samplings of out-of-tolerance supply (below V
SENSE
)
must occur at the IN pin to active NMI. Therefore, the
supply must be below the voltage sense point for ap-
proximately 100
μ
s or the comparator will reset. In this
way, power supply noise is removed from the monitoring
function preventing false trips. During a power–up, any
IN pin levels below V
TP
detected by the comparator are
disabled from reaching the NMI pin until V
CC
rises to
V
CCTP
. As a result, any potential active NMI will not be
initiated until V
CC
reaches V
CCTP
.
Removal of an active low level on the NMI pin is con-
trolled by the subsequent rise of the IN pin above V
TP
.
The initiation and removal of the NMI signal during pow-
er up depends on the relative voltage relationship be-
tween V
CC
and the IN pin voltage. Note that a fast slew-
ing power supply may cause the NMI to be virtually
non-existent on power up. This is of no consequence
however, since an RST will be active. The NMI voltage
will follow V
CC
down until V
CC
decays to V
BAT
. Once
V
CC
decays to VBAT, the NMI pin will enter a tri-state
mode.
ST INPUT TIMING
Figure 2
t
ST
t
TD
V
IH
ST
相关PDF资料
PDF描述
DS1239 MicroManager Chip(微管理器芯片)
DS1250AB 4096K Nonvolatile SRAM(4096K 非易失性静态RAM)
DS1250Y 4096K Nonvolatile SRAM(4096K 非易失性静态RAM)
DS1250W 3.3V 4096K Nonvolatile SRAM(3.3V 4096K 非易失性静态RAM)
DS1251Y 4096K NV SRAM with Phantom Clock(带幻影时钟的4096K NV 静态RAM)
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