参数资料
型号: DS1238A
厂商: DALLAS SEMICONDUCTOR
元件分类: 电源管理
英文描述: MicroManager(微管理器芯片)
中文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP16
封装: 0.300 INCH, DIP-16
文件页数: 8/13页
文件大小: 159K
代理商: DS1238A
DS1238A
022698 8/13
POWER SWITCHING
Figure 8
PF
GND
RST
GND
PF
To uP
From Decoder
To SRAM
+3V
Battery
DS1238A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DS1336
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
+5 V
DC
IN2
IN4
V
BAT02
OUT4
V
BATIN
V
CCO
V
CC
RST
CEI
CEO
PF
OUT5
IN5
V
BAT
To SRAM V
CC
V
CC
/IN1
OUT1
OUT2
OUT3
V
BAT01
IN3
Note: If freshness on the DS1238A is not used,
PF on the DS1336 may be tied to OUT1. This will
free IN4, OUT4, AND V
BAT01
for system use.
TIMING DIAGRAMS
This section provides a description of the timing dia-
grams shown in Figure 9 and Figure 10. Figure 9 illus-
trates the relationship for power down. As V
CC
falls, the
IN pin voltage drops below V
TP
. As a result, the proces-
sor is notified of an impending power failure via an active
NMI. This gives the processor time to save critical data
in nonvolatile SRAM. As the power falls further, V
CC
crosses V
CCTP
, the power monitor trip point. When V
CC
reaches V
CCTP
, and active RST and RST are given. At
this time, CEO is brought high to write protect the RAM.
When the V
CC
reaches V
BAT
, a power fail is issued via
the PF pin.
Figure 10 shows the power up sequence. As V
CC
slews
above V
BAT
, the PF pin is deactivated. An active reset
occurs as well as an NMI. Although the NMI may be
short due to slew rates, reset will be maintained for the
standard t
RPU
timeout period . At a later time, if the IN pin
falls below V
TP
, a new NMI will occur. If the processor
does not issue an ST, a watchdog reset will also occur.
The second NMI and RST are provided to illustrate
these possibilities.
相关PDF资料
PDF描述
DS1238 MicroManager(微管理器芯片)
DS1239 MicroManager Chip(微管理器芯片)
DS1250AB 4096K Nonvolatile SRAM(4096K 非易失性静态RAM)
DS1250Y 4096K Nonvolatile SRAM(4096K 非易失性静态RAM)
DS1250W 3.3V 4096K Nonvolatile SRAM(3.3V 4096K 非易失性静态RAM)
相关代理商/技术参数
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