参数资料
型号: DS1244W-120IND
英文描述: 256k NV SRAM with Phantom Clock
中文描述: 256k非易失SRAM与幻影时钟
文件页数: 12/19页
文件大小: 292K
代理商: DS1244W-120IND
ADS1244
SBAS273
12
www.ti.com
FIGURE 14. Self-Calibration Timing.
23
DRDY/DOUT
SCLK
1
24
t
9
25
26
23
22
21
0
Data ready after cal.
Cal begins.
SYMBOL
DESCRIPTION
MIN
MAX
UNITS
t
9(1)
First data ready after calibration.
209
210
ms
NOTE: (1) Values given for f
CLK
= 2.4576MHz. For different CLK frequencies, scale proportional to CLK
period.
SELF-CALIBRATION
The user can initiate self-calibration at any time, though in
many applications the ADS1244
s drift performance is good
enough that the self-calibration performing automatically at
power-up is all that is needed. To initiate a self-calibration,
apply at least two additional SCLKs after retrieving 24 bits of
data. Figure 14 shows the timing pattern. The 25th SCLK will
send
DRDY/DOUT
HIGH. The falling edge of the 26th SCLK
will begin the calibration cycle. Additional SCLK pulses may
be sent after the 26th SCLK, but try to minimize activity on
SCLK during calibration for best results.
When the calibration is complete,
DRDY/DOUT
will go LOW
indicating that new data is ready. There is no need to alter the
analog input signal applied to the ADS1244 during calibration,
the inputs pins are disconnected within the A/D converter and
the appropriate signals applied internally automatically. The
first conversion after a calibration is fully settled and valid for
use. The time required for a calibration depends on two
independent signals: the falling edge of SCLK and an internal
clock derived from CLK. Variations in the internal calibration
values will change the time required for calibration (t
9
) within
the range given by the MIN/MAX specs. t
12
and t
13
described
in the next section are affected likewise.
相关PDF资料
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DS1244WP-120IND 256k NV SRAM with Phantom Clock
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