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参数资料
| 型号： | DS1249W-150 |
| 厂商： | Maxim Integrated |
| 文件页数： | 2/8页 |
| 文件大小： | 0K |
| 描述： | IC NVSRAM 2MBIT 150NS 32DIP |
| 标准包装： | 11 |
| 格式 - 存储器： | RAM |
| 存储器类型： | NVSRAM（非易失 SRAM） |
| 存储容量： | 2M (256K x 8) |
| 速度： | 150ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 32-DIP 模块（0.600"，15.24mm） |
| 供应商设备封装： | 32-EDIP |
| 包装： | 管件 |
DS1249W
READ MODE
The DS1249 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 18 address inputs
(A 0 – A 17 ) defines which of the 262,144 bytes of data is accessed. Valid data will be available to the eight
data output drivers within t ACC (Access Time) after the last address input signal is stable, providing that
CE and OE access times are also satisfied. If OE and CE access times are not satisfied, then data access
must be measured from the later-occurring signal ( CE or OE ) and the limiting parameter is either t CO for
CE or t OE for OE rather than t ACC .
WRITE MODE
The DS1249 executes a write cycle whenever the WE and CE signals are active (low) after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle.
The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must be kept
valid throughout the write cycle. WE must return to the high state for a minimum recovery time (t WR )
before another cycle can be initiated. The OE control signal should be kept inactive (high) during write
cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active), then WE
will disable the outputs in t ODW from its falling edge.
DATA-RETENTION MODE
The DS1249W provides full functional capability for V CC greater than 3.0 volts and write protects by
2.8V. Data is maintained in the absence of V CC without any additional support circuitry. The nonvolatile
static RAMs constantly monitor V CC . Should the supply voltage decay, the NV SRAMs automatically
write protects themselves, all inputs become “don’t care,” and all outputs become high impedance. As
V CC falls below approximately 2.5V, a power-switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when V CC rises above approximately 2.5V, the power-switching
circuit connects external V CC to the RAM and disconnects the lithium energy source. Normal RAM
operation can resume after V CC exceeds 3.0V.
FRESHNESS SEAL
Each DS1249 device is shipped from Maxim with its lithium energy source disconnected, guaranteeing
full energy capacity. When V CC is first applied at a level greater than V TP , the lithium energy source is
enabled for battery backup operation.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1249W-150# | 功能描述:NVRAM 3.3V 2048K NV SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1249W-150-IND | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:3.3V 2048kb Nonvolatile SRAM |
| DS1249Y | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:2048k Nonvolatile SRAM |
| DS1249Y/AB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:2048K Nonvolatile SRAM |
| DS1249Y100 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:2048k Nonvolatile SRAM |
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