参数资料
型号: DS12C887A+
厂商: Maxim Integrated Products
文件页数: 7/22页
文件大小: 0K
描述: IC RTC W/RAM 128 BYTE 24-EDIP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 14
类型: 时钟/日历
特点: 警报器,夏令时,闰年,NVSRAM,方波输出
存储容量: 113B
时间格式: HH:MM:SS(12/24 小时)
数据格式: YY-MM-DD-dd
接口: 并联
电源电压: 4.5 V ~ 5.5 V
电压 - 电源,电池: 2.5 V ~ 4 V
工作温度: 0°C ~ 70°C
安装类型: 通孔
封装/外壳: 24-DIP 模块(0.600",15.24mm)
供应商设备封装: 24-EDIP
包装: 管件
产品目录页面: 1433 (CN2011-ZH PDF)
DS12885/DS12887/DS12887A/DS12C887/DS12C887A
Real-Time Clocks
____________________________________________________________________
15
Bit 7: Update-In-Progress (UIP). This bit is a status
flag that can be monitored. When the UIP bit is a 1, the
update transfer occurs soon. When UIP is a 0, the
update transfer does not occur for at least 244s. The
time, calendar, and alarm information in RAM is fully
available for access when the UIP bit is 0. The UIP bit is
read-only and is not affected by RESET. Writing the
SET bit in Register B to a 1 inhibits any update transfer
and clears the UIP status bit.
Bits 6, 5, and 4: DV2, DV1, DV0. These three bits are
used to turn the oscillator on or off and to reset the
countdown chain. A pattern of 010 is the only combina-
tion of bits that turn the oscillator on and allow the RTC
to keep time. A pattern of 11x enables the oscillator but
holds the countdown chain in reset. The next update
occurs at 500ms after a pattern of 010 is written to DV0,
DV1, and DV2.
Bits 3 to 0: Rate Selector (RS3, RS2, RS1, RS0).
These four rate-selection bits select one of the 13 taps
on the 15-stage divider or disable the divider output.
The tap selected can be used to generate an output
square wave (SQW pin) and/or a periodic interrupt. The
user can do one of the following:
1)
Enable the interrupt with the PIE bit;
2)
Enable the SQW output pin with the SQWE bit;
3)
Enable both at the same time and the same rate;
or
4)
Enable neither.
Table 3 lists the periodic interrupt rates and the square-
wave frequencies that can be chosen with the RS bits.
These four read/write bits are not affected by RESET.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
UIP
DV2
DV1
DV0
RS3
RS2
RS1
RS0
Control Register A
Control Registers
The real-time clocks have four control registers that are
accessible at all times, even during the update cycle.
MSB
LSB
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