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参数资料
| 型号： | DS1350WP-150+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/10页 |
| 文件大小： | 0K |
| 描述： | IC NVSRAM 4MBIT 150NS 34PCM |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 格式 - 存储器： | RAM |
| 存储器类型： | NVSRAM（非易失 SRAM） |
| 存储容量： | 4M (512K x 8) |
| 速度： | 150ns |
| 接口： | 并联 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 34-PowerCap? 模块 |
| 供应商设备封装： | 34-PowerCap 模块 |
| 包装： | 管件 |
DS1350W
READ MODE
The DS1350W executes a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs
(A 0 - A 18 ) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t ACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later occurring signal ( CE or OE ) and the limiting
parameter is either t CO for CE or t OE for OE rather than address access.
WRITE MODE
The DS1350W executes a write cycle whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(t WR ) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE active) then
WE will disable the outputs in t ODW from its falling edge.
DATA RETENTION MODE
The DS1350W provides full functional capability for V CC greater than 3.0 volts and write protects by 2.8
volts. Data is maintained in the absence of V CC without any additional support circuitry. The nonvolatile
static RAMs constantly monitor V CC . Should the supply voltage decay, the NV SRAMs automatically
write protect themselves, all inputs become “don’t care,” and all outputs become high impedance. As V CC
falls below approximately 2.5 volts, the power switching circuit connects the lithium energy source to
RAM to retain data. During power-up, when V CC rises above approximately 2.5 volts, the power
switching circuit connects external V CC to the RAM and disconnects the lithium energy source. Normal
RAM operation can resume after V CC exceeds 3.0 volts.
SYSTEM POWER MONITORING
The DS1350W has the ability to monitor the external V CC power supply. When an out-of-tolerance power
supply condition is detected, the NV SRAM warns a processor-based system of impending power failure
by asserting RST . On power-up, RST is held active for 200 ms nominal to prevent system operation
during power-on transients and to allow t REC to elapse. RST has an open-drain output driver.
BATTERY MONITORING
The DS1350W automatically performs periodic battery voltage monitoring on a 24-hour time interval.
Such monitoring begins within t REC after V CC rises above V TP and is suspended when power failure
occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1 M Ω test resistor for 1
second. During this 1 second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output BW is asserted. Once asserted, BW remains active until the module is replaced.
The battery is still retested after each V CC power-up, however, even if BW is active. If the battery voltage
is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing
resumes. BW has an open-drain output driver.
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| DS1250W-100IND+ | IC NVSRAM 4MBIT 100NS 32DIP |
| DS1350YP-100+ | IC NVSRAM 4MBIT 100NS 34PCM |
| DS1350ABP-100+ | IC NVSRAM 4MBIT 100NS 34PCM |
| DS1250AB-100IND+ | IC NVSRAM 4096KBIT 100NS 32DIP |
| DS1250Y-100IND+ | IC NVSRAM 4MBIT 100NS 32DIP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1350WP-150+ | 功能描述:NVRAM 3.3V 4096K NV SRAM w/Battery Monitor RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1350WP-150IND | 功能描述:IC NVSRAM 4MBIT 150NS 34PCM RoHS:否 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:150 系列:- 格式 - 存储器:EEPROMs - 串行 存储器类型:EEPROM 存储容量:4K (2 x 256 x 8) 速度:400kHz 接口:I²C，2 线串口 电源电压:2.5 V ~ 5.5 V 工作温度:-40°C ~ 85°C 封装/外壳:8-VFDFN 裸露焊盘 供应商设备封装:8-DFN（2x3） 包装:管件 产品目录页面:1445 (CN2011-ZH PDF) |
| DS1350WP-150-IND | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:3.3V 4096K Nonvolatile SRAM with Battery Monitor |
| DS1350Y | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:4096k Nonvolatile SRAM with Battery Monitor |
| DS1350Y/AB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:4096k Nonvolatile SRAM with Battery Monitor |
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