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参数资料
| 型号： | DS1350YP-70IND+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/10页 |
| 文件大小： | 0K |
| 描述： | IC NVSRAM 4MBIT 70NS 34PCM |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 格式 - 存储器： | RAM |
| 存储器类型： | NVSRAM（非易失 SRAM） |
| 存储容量： | 4M (512K x 8) |
| 速度： | 70ns |
| 接口： | 并联 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 34-PowerCap? 模块 |
| 供应商设备封装： | 34-PowerCap 模块 |
| 包装： | 管件 |
DS1350Y/AB
READ MODE
The DS1350 devices execute a read cycle whenever WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The unique address specified by the 19 address inputs
(A 0 -A 18 ) defines which of the 524,288 bytes of data is to be accessed. Valid data will be available to the
eight data output drivers within t ACC (Access Time) after the last address input signal is stable, providing
that CE and OE (Output Enable) access times are also satisfied. If OE and CE access times are not
satisfied, then data access must be measured from the later-occurring signal ( CE or OE ) and the limiting
parameter is either t CO for CE or t OE for OE rather than address access.
WRITE MODE
The DS1350 devices execute a write cycle whenever the WE and CE signals are in the active (low) state
after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of
the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (t WR ) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE
active) then WE will disable the outputs in t ODW from its falling edge.
DATA RETENTION MODE
The DS1350AB provides full functional capability for V CC greater than 4.75V and write protects by 4.5V.
The DS1350Y provides full functional capability for V CC greater than 4.5V and write protects by 4.25V.
Data is maintained in the absence of V CC without any additional support circuitry. The NV SRAMs
constantly monitor V CC . Should the supply voltage decay, the NV SRAMs automatically write protect
themselves, all inputs become “don’t care,” and all outputs become high-impedance. As V CC falls below
approximately 2.7V, the power switching circuit connects the lithium energy source to RAM to retain
data. During power-up, when V CC rises above approximately 2.7V, the power switching circuit connects
external V CC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume
after V CC exceeds 4.75V for the DS1350AB and 4.5V for the DS1350Y.
SYSTEM POWER MONITORING
DS1350 devices have the ability to monitor the external V CC power supply. When an out-of-tolerance
power supply condition is detected, the NV SRAMs warn a processor-based system of impending power
failure by asserting RST . On power-up, RST is held active for 200ms nominal to prevent system
operation during power-on transients and to allow t REC to elapse. RST has an open drain output driver.
BATTERY MONITORING
The DS1350 devices automatically perform periodic battery voltage monitoring on a 24-hour time
interval. Such monitoring begins within t REC after V CC rises above V TP and is suspended when power
failure occurs.
After each 24-hour period has elapsed, the battery is connected to an internal 1M ? test resistor for one
second. During this one second, if battery voltage falls below the battery voltage trip point (2.6V), the
battery warning output BW is asserted. Once asserted, BW remains active until the module is replaced.
The battery is still retested after each V CC power-up, however, even if BW is active. If the battery voltage
is found to be higher than 2.6V during such testing, BW is de-asserted and regular 24-hour testing
resumes. BW has an open drain output driver.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1350YP-70IND+ | 功能描述:NVRAM 4096K NV SRAM w/Battery Monitor RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1350YP-C01 | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1351 | 制造商:MA-COM 制造商全称:M/A-COM Technology Solutions, Inc. 功能描述:Shielded Drum Core Inductors |
| DS1351-100M | 功能描述:INDUCTOR 10UH 2A 20% 1351 RoHS:否 类别:电感器，线圈，扼流圈 >> 固定式 系列:DS1351 标准包装:500 系列:1331 电感:1.2µH 电流:247mA 电流 - 饱和:247mA 电流 - 温升:- 类型:铁芯体 容差:±10% 屏蔽:屏蔽 DC 电阻(DCR):最大 730 毫欧 Q因子@频率:40 @ 7.9MHz 频率 - 自谐振:130MHz 材料 - 芯体:铁 封装/外壳:0.312" L x 0.115" W x 0.135" H（7.94mm x 2.92mm x 3.43mm） 安装类型:表面贴装 包装:带卷 (TR) 工作温度:-55°C ~ 105°C 频率 - 测试:7.9MHz |
| DS1351-101M | 功能描述:INDUCTOR 100UH 20% SMD 1351 RoHS:否 类别:电感器，线圈，扼流圈 >> 固定式 系列:DS1351 标准包装:500 系列:1331 电感:1.2µH 电流:247mA 电流 - 饱和:247mA 电流 - 温升:- 类型:铁芯体 容差:±10% 屏蔽:屏蔽 DC 电阻(DCR):最大 730 毫欧 Q因子@频率:40 @ 7.9MHz 频率 - 自谐振:130MHz 材料 - 芯体:铁 封装/外壳:0.312" L x 0.115" W x 0.135" H（7.94mm x 2.92mm x 3.43mm） 安装类型:表面贴装 包装:带卷 (TR) 工作温度:-55°C ~ 105°C 频率 - 测试:7.9MHz |
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