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参数资料
| 型号： | DS1371 |
| 厂商： | Maxim Integrated Products, Inc. |
| 元件分类： | 通用总线功能 |
| 英文描述： | 2-Wire, 32-Bit Binary Counter Watchdog Clock |
| 中文描述： | I²C、32位二进制计数器看门狗时钟 |
| 文件页数： | 10/14页 |
| 文件大小： | 966K |
| 代理商： | DS1371 |
DS1371
10 of 14
Special Purpose Registers
The DS1371 has two additional registers (07h–08h) that control the WD/
ALM
counter, square-wave
output, and interrupts.
Control Register (07h)
Bit #
7
6
5
Name
EOSC
WACE
WD/
ALM
Default
0
0
0
Bit 7/Enable Oscillator (
EOSC
).
When set to logic 0, the oscillator is started. When set to logic 1, the
oscillator is stopped. When this bit is set to a logic 1, the oscillator is stopped and the DS1371 is placed
into a low-power standby mode (I
DDR
). This bit is clear (logic 0) when power is first applied.
Bit 6/WD/
ALM
Counter Enable (WACE).
When set to logic 1, the WD/
ALM
counter is enabled. When
set to logic 0, the WD/
ALM
counter is disabled, and the 24-bits can be used as general-purpose RAM.
This bit is clear (logic 0) when power is first applied.
Bit 5/WD/
ALM
Counter Select (WD/
ALM
).
When set to logic 0, the counter decrements every second
until it reaches 0 and is then reloaded and restarted. When set to logic 1, the WD/
ALM
counter
decrements every 1/4096 of a second (approximately every 244μs) until it reaches 0, sets the AF bit in the
status register, and stops. If any of the WD/
ALM
counter registers are read or written, or a rising edge on
the WDS pin occurs before the counter reaches 0, the counter is reloaded and restarted. This bit is clear
(logic 0) when power is first applied.
Bit 3/Interrupt Control (INTCN).
This bit controls the SQW/
INT
signal. When the INTCN bit is set to
logic 0, a square wave is output on the SQW/
INT
pin whose frequency is defined by bits RS2 and RS1.
The oscillator must also be enabled for the square wave to be output. When the INTCN bit is set to logic
1, then this permits the alarm flag bit in the status register to assert SQW/
INT
(provided that the alarm is
also enabled). The alarm flag is always set, regardless of the state of the INTCN bit. The INTCN bit is set
to logic 0 when power is first applied.
Bits 2, 1/Rate Select 1 and 2 (RS2 and RS1).
These bits control the frequency of the square-wave output
when the square wave has been enabled. Table 3 shows the square-wave frequencies that can be selected
with the RS bits. These bits are both set (logic 1) when power is first applied.
Bit 0/Alarm Interrupt Enable (AIE).
When set to logic 1, this bit permits the AF bit in the status
register to assert SQW/
INT
(when INTCN = 1). When set to logic 0 or INTCN is set to logic 0, the AF bit
does not initiate the SQW/
INT
signal. If the WD/
ALM
bit is set to a logic 1 and the AF flag is set, writing
AIE to a 0 does not truncate the 250ms pulse on the SQW/
INT
pin. The AIE bit is at logic 0 when power
is first applied.
Table 3. Square-Wave Output Frequency
SQUARE-WAVE OUTPUT
FREQUENCY
0
0
1Hz
0
1
4.096kHz
1
0
8.192kHz
1
1
32.768kHz
4
0
0
3
2
1
0
INTCN
0
RS2
1
RS1
1
AIE
0
RS2
RS1
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1371_07 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:I2C, 32-Bit Binary Counter |
| DS1371U | 功能描述:实时时钟 I2C 32 bit Binary Counter RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS1371U/C01 | 制造商:Maxim Integrated Products 功能描述:SERIAL RTC USOP DEXCOM - Rail/Tube |
| DS1371U/T&R | 功能描述:实时时钟 I2C 32 bit Binary Counter RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS1371U+ | 功能描述:实时时钟 I2C 32 bit Binary Counter RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
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