参数资料
型号: DS1372
厂商: Maxim Integrated Products, Inc.
元件分类: 通用总线功能
英文描述: I2C, 32-Bit, Binary Counter Clock with 64-Bit ID
中文描述: I²C、32位、二进制计数时钟,具有64位ID
文件页数: 2/12页
文件大小: 173K
代理商: DS1372
D
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground…..-0.3V to +6.0V
Continuous Power Dissipation (T
A
= +70°C)
(derate 4.5mW/°C above +70°C) …………………….....360mW
RECOMMENDED DC ELECTRICAL CHARACTERISTICS
(V
CC
= 2.4V to 5.5V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature Range
(noncondensing)……. .......................................-40°C to +85°C
Storage Temperature Range…………………….-55°C to +125°C
Soldering Temperature………….......See IPC/JEDEC J-STD-020
specification.
PARAMETER
SYMBOL
CONDITIONS
MIN
2.4
TYP
MAX
5.5
UNITS
Operating voltage range (Notes 2 and 3)
Timekeeping operating range
(Notes 2 and 4)
(Note 3)
EOSC
= 0
(Notes 4 and 5)
Supply Voltage
V
CC
1.3
5.5
V
Active Supply Current
Standby Current
(Oscillator Enabled)
Data Retention
(Oscillator Disabled)
Input Logic 1
AD0, SCL, SDA
Input Logic 0
AD0, SCL, SDA
Input Leakage
AD0, SCL, SDA, SQW/
INT
I
CCA
35
600
400
90
1300
800
μA
SQW = 32kHz
SQW = 0
I
CCS
nA
I
DDR
EOSC
= 1 (Note 4)
25
100
nA
V
IH
(Note 2)
0.7 x
V
CC
V
CC
+
0.3
0.3 x
V
CC
V
V
IL
(Note 2)
-0.3
V
I
LI
SDA, SQW/
INT
high impedance
-1
+1
μA
V
OL
= 0.4V (V
CC
> 2.4V), SDA, SQW/
INT
V
OL
= 0.2V
CC
(1.3V < V
CC
< 2.4V), SQW/
INT
3
Output Logic 0
I
OL
0.250
mA
ELECTRICAL CHARACTERISTICS
(V
CC
= 2.4V to 5.5V, T
A
= -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
100
0.04
1.3
4.7
0.6
4.0
1.3
4.7
0.6
4.0
0.6
4.7
0
0
TYP
MAX
400
100.00
0.9
UNITS
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
Fast mode
Standard mode
SCL Clock Frequency (Note 6)
f
SCL
kHz
Bus-Free Time Between a STOP
and START Condition
Hold Time (Repeated) START
Condition (Note 7)
t
BUF
μs
t
HD:STA
μs
Low Period of SCL Clock
t
LOW
μs
High Period of SCL Clock
t
HIGH
μs
Setup Time for Repeated START
Condition
t
SU:STA
μs
Data Hold Time (Notes 8 and 9)
t
HD:DAT
μs
I
2
C, 32-Bit, Binary Counter Clock with 64-Bit ID
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